/** * \file drm_stub.c * Stub support * * \author Rickard E. (Rik) Faith */ /* * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org * * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include "drmP.h" #include "drm_core.h" unsigned int drm_cards_limit = 16; /* Enough for one machine */ unsigned int drm_debug = 0; /* 1 to enable debug output */ EXPORT_SYMBOL(drm_debug); MODULE_AUTHOR(CORE_AUTHOR); MODULE_DESCRIPTION(CORE_DESC); MODULE_LICENSE("GPL and additional rights"); MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards"); MODULE_PARM_DESC(debug, "Enable debug output"); module_param_named(cards_limit, drm_cards_limit, int, S_IRUGO); module_param_named(debug, drm_debug, int, S_IRUGO|S_IWUGO); drm_head_t **drm_heads; struct drm_sysfs_class *drm_class; struct proc_dir_entry *drm_proc_root; drm_cache_t drm_cache = { .mm = NULL, .fence_object = NULL }; static int drm_fill_in_dev(drm_device_t * dev, struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver *driver) { int retcode; spin_lock_init(&dev->count_lock); spin_lock_init(&dev->drw_lock); spin_lock_init(&dev->tasklet_lock); init_timer(&dev->timer); mutex_init(&dev->struct_mutex); mutex_init(&dev->ctxlist_mutex); mutex_init(&dev->bm.init_mutex); dev->pdev = pdev; dev->pci_device = pdev->device; dev->pci_vendor = pdev->vendor; #ifdef __alpha__ dev->hose = pdev->sysdata; #endif dev->irq = pdev->irq; if (drm_ht_create(&dev->map_hash, DRM_MAP_HASH_ORDER)) { drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); return -ENOMEM; } if (drm_mm_init(&dev->offset_manager, DRM_FILE_PAGE_OFFSET_START, DRM_FILE_PAGE_OFFSET_SIZE)) { drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); drm_ht_remove(&dev->map_hash); return -ENOMEM; } if (drm_ht_create(&dev->object_hash, DRM_OBJECT_HASH_ORDER)) { drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); drm_ht_remove(&dev->map_hash); drm_mm_takedown(&dev->offset_manager); return -ENOMEM; } dev->maplist = drm_calloc(1, sizeof(*dev->maplist), DRM_MEM_MAPS); if (dev->maplist == NULL) return -ENOMEM; INIT_LIST_HEAD(&dev->maplist->head); /* the DRM has 6 counters */ dev->counters = 6; dev->types[0] = _DRM_STAT_LOCK; dev->types[1] = _DRM_STAT_OPENS; dev->types[2] = _DRM_STAT_CLOSES; dev->types[3] = _DRM_STAT_IOCTLS; dev->types[4] = _DRM_STAT_LOCKS; dev->types[5] = _DRM_STAT_UNLOCKS; dev->driver = driver; if (dev->driver->load) if ((retcode = dev->driver->load(dev, ent->driver_data))) goto error_out_unreg; if (drm_core_has_AGP(dev)) { if (drm_device_is_agp(dev)) dev->agp = drm_agp_init(dev); if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) && (dev->agp == NULL)) { DRM_ERROR("Cannot initialize the agpgart module.\n"); retcode = -EINVAL; goto error_out_unreg; } if (drm_core_has_MTRR(dev)) { if (dev->agp) dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, dev->agp->agp_info.aper_size * 1024 * 1024, MTRR_TYPE_WRCOMB, 1); } } retcode = drm_ctxbitmap_init(dev); if (retcode) { DRM_ERROR("Cannot allocate memory for context bitmap.\n"); goto error_out_unreg; } drm_fence_manager_init(dev); return 0; error_out_unreg: drm_lastclose(dev); return retcode; } /** * Get a secondary minor number. * * \param dev device data structure * \param sec-minor structure to hold the assigned minor * \return negative number on failure. * * Search an empty entry and initialize it to the given parameters, and * create the proc init entry via proc_init(). This routines assigns * minor numbers to secondary heads of multi-headed cards */ static int drm_get_head(drm_device_t * dev, drm_head_t * head) { drm_head_t **heads = drm_heads; int ret; int minor; DRM_DEBUG("\n"); for (minor = 0; minor < drm_cards_limit; minor++, heads++) { if (!*heads) { *head = (drm_head_t) { .dev = dev, .device = MKDEV(DRM_MAJOR, minor), .minor = minor, }; if ((ret = drm_proc_init(dev, minor, drm_proc_root, &head->dev_root))) { printk(KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); goto err_g1; } head->dev_class = drm_sysfs_device_add(drm_class, head); if (IS_ERR(head->dev_class)) { printk(KERN_ERR "DRM: Error sysfs_device_add.\n"); ret = PTR_ERR(head->dev_class); goto err_g2; } *heads = head; DRM_DEBUG("new minor assigned %d\n", minor); return 0; } } DRM_ERROR("out of minors\n"); return -ENOMEM; err_g2: drm_proc_cleanup(minor, drm_proc_root, head->dev_root); err_g1: *head = (drm_head_t) { .dev = NULL}; return ret; } /** * Register. * * \param pdev - PCI device structure * \param ent entry from the PCI ID table with device type flags * \return zero on success or a negative number on failure. * * Attempt to gets inter module "drm" information. If we are first * then register the character device and inter module information. * Try and register, if we fail to register, backout previous work. */ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver *driver) { drm_device_t *dev; int ret; DRM_DEBUG("\n"); dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB); if (!dev) return -ENOMEM; if (!drm_fb_loaded) { pci_set_drvdata(pdev, dev); pci_request_regions(pdev, driver->pci_driver.name); } pci_enable_device(pdev); pci_set_master(pdev); if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { printk(KERN_ERR "DRM: fill_in_dev failed\n"); goto err_g1; } if ((ret = drm_get_head(dev, &dev->primary))) goto err_g1; DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", driver->name, driver->major, driver->minor, driver->patchlevel, driver->date, dev->primary.minor, pci_pretty_name(dev->pdev)); return 0; err_g1: if (!drm_fb_loaded) { pci_set_drvdata(pdev, NULL); pci_release_regions(pdev); pci_disable_device(pdev); } drm_free(dev, sizeof(*dev), DRM_MEM_STUB); printk(KERN_ERR "DRM: drm_get_dev failed.\n"); return ret; } EXPORT_SYMBOL(drm_get_dev); /** * Put a device minor number. * * \param dev device data structure * \return always zero * * Cleans up the proc resources. If it is the last minor then release the foreign * "drm" data, otherwise unregisters the "drm" data, frees the dev list and * unregisters the character device. */ int drm_put_dev(drm_device_t * dev) { DRM_DEBUG("release primary %s\n", dev->driver->pci_driver.name); if (dev->unique) { drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER); dev->unique = NULL; dev->unique_len = 0; } if (dev->devname) { drm_free(dev->devname, strlen(dev->devname) + 1, DRM_MEM_DRIVER); dev->devname = NULL; } drm_free(dev, sizeof(*dev), DRM_MEM_STUB); return 0; } /** * Put a secondary minor number. * * \param sec_minor - structure to be released * \return always zero * * Cleans up the proc resources. Not legal for this to be the * last minor released. * */ int drm_put_head(drm_head_t * head) { int minor = head->minor; DRM_DEBUG("release secondary minor %d\n", minor); drm_proc_cleanup(minor, drm_proc_root, head->dev_root); drm_sysfs_device_remove(head->dev_class); *head = (drm_head_t){.dev = NULL}; drm_heads[minor] = NULL; return 0; } 78'>178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

/*
 * NV20
 * -----
 * There are 3 families :
 * NV20 is 0x10de:0x020*
 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
 * NV2A is 0x10de:0x02A0
 *
 * NV30
 * -----
 * There are 3 families :
 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
 * NV34 is 0x10de:0x032*
 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
 *
 * Not seen in the wild, no dumps (probably NV35) :
 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
 *
 */

#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV2A_GRCTX_SIZE (3500*4)

#define NV30_31_GRCTX_SIZE (24392)
#define NV34_GRCTX_SIZE    (18140)
#define NV35_36_GRCTX_SIZE (22396)

static void nv20_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
+0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
+0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
+0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
+0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
+0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
+0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000

+0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
+0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
	for (i = 0; i < 16; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
	INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff);
	INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
	INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000);
	INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);

/*
...
+0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	for (i = 0; i < 0x880; i += 0x10) {
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
	}

/*
write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
+0x00742fbc: 3f800000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);

/*
write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
+0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x0074301c: 00000000 bf800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
	INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
	INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);

/*
write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
+0x00742fcc: 00000000 3f800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);

/*
write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
+0x0074302c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
+0x00743c9c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
+0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);

/*
write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
+0x00743c6c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
+0x00743ccc: 00000000 000003f8 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);

/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
	INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);

/*
write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
+0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
	for (i = 0; i < 8; ++i)
		INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
}

static void nv2a_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x33c/4, 0xffff0000);
	for(i = 0x3a0; i< 0x3a8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x47c/4, 0x00000101);
	INSTANCE_WR(ctx, 0x490/4, 0x00000111);
	INSTANCE_WR(ctx, 0x4a8/4, 0x44400000);
	for(i = 0x4d4; i< 0x4e4; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x4f4; i< 0x504; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080000);
	for(i = 0x50c; i< 0x51c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x51c; i< 0x52c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x000105b8);
	for(i = 0x52c; i< 0x53c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	for(i = 0x55c; i< 0x59c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x5fc/4, 0x00000001);
	INSTANCE_WR(ctx, 0x604/4, 0x00004000);
	INSTANCE_WR(ctx, 0x610/4, 0x00000001);
	INSTANCE_WR(ctx, 0x618/4, 0x00040000);
	INSTANCE_WR(ctx, 0x61c/4, 0x00010000);

	for (i=0x1a9c; i <= 0x22fc/4; i += 32) {
		INSTANCE_WR(ctx, i/4    , 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}

	INSTANCE_WR(ctx, 0x269c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26dc/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x26ec/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x2700/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x3024/4, 0x000fe000);
	INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8);
	INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000);
	for(i = 0x341c; i< 0x343c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x001c527c);
}

static void nv25_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8

+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d1c: 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
	INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
	INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
	INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
	INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);