/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
/*
* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*/
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "r300_reg.h"
#define RADEON_FIFO_DEBUG 0
static int radeon_do_cleanup_cp(struct drm_device * dev);
/* CP microcode (from ATI) */
static const u32 R200_cp_microcode[][2] = {
{0x21007000, 0000000000},
{0x20007000, 0000000000},
{0x000000ab, 0x00000004},
{0x000000af, 0x00000004},
{0x66544a49, 0000000000},
{0x49494174, 0000000000},
{0x54517d83, 0000000000},
{0x498d8b64, 0000000000},
{0x49494949, 0000000000},
{0x49da493c, 0000000000},
{0x49989898, 0000000000},
{0xd34949d5, 0000000000},
{0x9dc90e11, 0000000000},
{0xce9b9b9b, 0000000000},
{0x000f0000, 0x00000016},
{0x352e232c, 0000000000},
{0x00000013, 0x00000004},
{0x000f0000, 0x00000016},
{0x352e272c, 0000000000},
{0x000f0001, 0x00000016},
{0x3239362f, 0000000000},
{0x000077ef, 0x00000002},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
|