/* * Copyright © 2008 Jérôme Glisse * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. */ /* * Authors: * Aapo Tahkola * Nicolai Haehnle * Jérôme Glisse */ #include #include #include #include #include #include "radeon_cs.h" #include "radeon_cs_gem.h" #include "radeon_bo_gem.h" #include "drm.h" #include "xf86drm.h" #include "radeon_drm.h" #pragma pack(1) struct cs_reloc_gem { uint32_t handle; uint32_t read_domain; uint32_t write_domain; uint32_t flags; }; #pragma pack() #define RELOC_SIZE (sizeof(struct cs_reloc_gem) / sizeof(uint32_t)) struct cs_gem { struct radeon_cs base; struct drm_radeon_cs cs; struct drm_radeon_cs_chunk chunks[2]; unsigned nrelocs; uint32_t *relocs; struct radeon_bo **relocs_bo; }; static struct radeon_cs *cs_gem_create(struct radeon_cs_manager *csm, uint32_t ndw) { struct cs_gem *csg; /* max cmd buffer size is 64Kb */ if (ndw > (64 * 1024 / 4)) { return NULL; } csg = (struct cs_gem*)calloc(1, sizeof(struct cs_gem)); if (csg == NULL) { return NULL; } csg->base.csm = csm; csg->base.ndw = 64 * 1024 / 4; csg->base.packets = (uint32_t*)calloc(1, 64 * 1024); if (csg->base.packets == NULL) { free(csg); return NULL; } csg->base.relocs_total_size = 0; csg->base.crelocs = 0; csg->nrelocs = 4096 / (4 * 4) ; csg->relocs_bo = (struct radeon_bo**)calloc(1, csg->nrelocs*sizeof(void*)); if (csg->relocs_bo == NULL) { free(csg->base.packets); free(csg); return NULL; } csg->base.relocs = csg->relocs = (uint32_t*)calloc(1, 4096); if (csg->relocs == NULL) { free(csg->relocs_bo); free(csg->base.packets); free(csg); return NULL; } csg->chunks[0].chunk_id = RADEON_CHUNK_ID_IB; csg->chunks[0].length_dw = 0; csg->chunks[0].chunk_data = (uint64_t)(uintptr_t)csg->base.packets; csg->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; csg->chunks[1].length_dw = 0; csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs; return (struct radeon_cs*)csg; } static int cs_gem_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, uint32_t flags) { struct cs_gem *csg = (struct cs_gem*)cs; struct cs_reloc_gem *reloc; uint32_t idx; unsigned i; assert(bo->space_accounted); /* check domains */ if ((read_domain && write_domain) || (!read_domain && !write_domain)) { /* in one CS a bo can only be in read or write domain but not * in read & write domain at the same sime */ return -EINVAL; } if (read_domain == RADEON_GEM_DOMAIN_CPU) { return -EINVAL; } if (write_domain == RADEON_GEM_DOMAIN_CPU) { return -EINVAL; } /* check if bo is already referenced */ for(i = 0; i < cs->crelocs; i++) { idx = i * RELOC_SIZE; reloc = (struct cs_reloc_gem*)&csg->relocs[idx]; if (reloc->handle == bo->handle) { /* Check domains must be in read or write. As we check already * checked that in argument one of the read or write domain was * set we only need to check that if previous reloc as the read * domain set then the read_domain should also be set for this * new relocation. */ /* the DDX expects to read and write from same pixmap */ if (write_domain && (reloc->read_domain & write_domain)) { reloc->read_domain = 0; reloc->write_domain = write_domain; } else if (read_domain & reloc->write_domain) { reloc->read_domain = 0; } else { if (write_domain != reloc->write_domain) return -EINVAL; if (read_domain != reloc->read_domain) return -EINVAL; } reloc->read_domain |= read_domain; reloc->write_domain |= write_domain; /* update flags */ reloc->flags |= (flags & reloc->flags); /* write relocation packet */ radeon_cs_write_dword(cs, 0xc0001000); radeon_cs_write_dword(cs, idx); return 0; } } /* new relocation */ if (csg->base.crelocs >= csg->nrelocs) { /* allocate more memory (TODO: should use a slab allocatore maybe) */ uint32_t *tmp, size; size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*)); tmp = (uint32_t*)realloc(csg->relocs_bo, size); if (tmp == NULL) { return -ENOMEM; } csg->relocs_bo = (struct radeon_bo**)tmp; size = ((csg->nrelocs + 1) * RELOC_SIZE * 4); tmp = (uint32_t*)realloc(csg->relocs, size); if (tmp == NULL) { return -ENOMEM; } cs->relocs = csg->relocs = tmp; csg->nrelocs += 1; csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs; } csg->relocs_bo[csg->base.crelocs] = bo; idx = (csg->base.crelocs++) * RELOC_SIZE; reloc = (struct cs_reloc_gem*)&csg->relocs[idx]; reloc->handle = bo->handle; reloc->read_domain = read_domain; reloc->write_domain = write_domain; reloc->flags = flags; csg->chunks[1].length_dw += RELOC_SIZE; radeon_bo_ref(bo); cs->relocs_total_size += bo->size; radeon_cs_write_dword(cs, 0xc0001000); radeon_cs_write_dword(cs, idx); return 0; } static int cs_gem_begin(struct radeon_cs *cs, uint32_t ndw, const char *file, const char *func, int line) { if (cs->section) { fprintf(stderr, "CS already in a section(%s,%s,%d)\n", cs->section_file, cs->section_func, cs->section_line); fprintf(stderr, "CS can't start section(%s,%s,%d)\n", file, func, line); return -EPIPE; } cs->section = 1; cs->section_ndw = ndw; cs->section_cdw = 0; cs->section_file = file; cs->section_func = func; cs->section_line = line; if (cs->cdw + ndw > cs->ndw) { uint32_t tmp, *ptr; tmp = (cs->ndw + 1 + 0x3FF) & (~0x3FF); ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); if (ptr == NULL) { return -ENOMEM; } cs->packets = ptr; cs->ndw = tmp; } return 0; } static int cs_gem_end(struct radeon_cs *cs, const char *file, const char *func, int line) { if (!cs->section) { fprintf(stderr, "CS no section to end at (%s,%s,%d)\n", file, func, line); return -EPIPE; } cs->section = 0; if (cs->section_ndw != cs->section_cdw) { fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); fprintf(stderr, "CS section end at (%s,%s,%d)\n", file, func, line); return -EPIPE; } return 0; } static int cs_gem_emit(struct radeon_cs *cs) { struct cs_gem *csg = (struct cs_gem*)cs; uint64_t chunk_array[2]; unsigned i; int r; csg->chunks[0].length_dw = cs->cdw; chunk_array[0] = (uint64_t)(uintptr_t)&csg->chunks[0]; chunk_array[1] = (uint64_t)(uintptr_t)&csg->chunks[1]; csg->cs.num_chunks = 2; csg->cs.chunks = (uint64_t)(uintptr_t)chunk_array; r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS, &csg->cs, sizeof(struct drm_radeon_cs)); for (i = 0; i < csg->base.crelocs; i++) { csg->relocs_bo[i]->space_accounted = 0; radeon_bo_unref(csg->relocs_bo[i]); csg->relocs_bo[i] = NULL; } cs->csm->read_used = 0; cs->csm->vram_write_used = 0; cs->csm->gart_write_used = 0; return r; } static int cs_gem_destroy(struct radeon_cs *cs) { struct cs_gem *csg = (struct cs_gem*)cs; free(csg->relocs_bo); free(cs->relocs); free(cs->packets); free(cs); return 0; } static int cs_gem_erase(struct radeon_cs *cs) { struct cs_gem *csg = (struct cs_gem*)cs; unsigned i; if (csg->relocs_bo) { for (i = 0; i < csg->base.crelocs; i++) { if (csg->relocs_bo[i]) { radeon_bo_unref(csg->relocs_bo[i]); csg->relocs_bo[i] = NULL; } } } cs->relocs_total_size = 0; cs->cdw = 0; cs->section = 0; cs->crelocs = 0; csg->chunks[0].length_dw = 0; csg->chunks[1].length_dw = 0; return 0; } static int cs_gem_need_flush(struct radeon_cs *cs) { return 0; //(cs->relocs_total_size > (32*1024*1024)); } #define PACKET_TYPE0 0 #define PACKET_TYPE1 1 #define PACKET_TYPE2 2 #define PACKET_TYPE3 3 #define PACKET3_NOP 0x10 #define PACKET3_SET_SCISSORS 0x1E #define PACKET3_3D_DRAW_VBUF 0x28 #define PACKET3_3D_DRAW_IMMD 0x29 #define PACKET3_3D_DRAW_INDX 0x2A #define PACKET3_3D_LOAD_VBPNTR 0x2F #define PACKET3_INDX_BUFFER 0x33 #define PACKET3_3D_DRAW_VBUF_2 0x34 #define PACKET3_3D_DRAW_IMMD_2 0x35 #define PACKET3_3D_DRAW_INDX_2 0x36 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) static void cs_gem_print(struct radeon_cs *cs, FILE *file) { unsigned opcode; unsigned reg; unsigned cnt; unsigned int i, j; for (i = 0; i < cs->cdw;) { cnt = CP_PACKET_GET_COUNT(cs->packets[i]) + 1; switch (CP_PACKET_GET_TYPE(cs->packets[i])) { case PACKET_TYPE0: fprintf(file, "Pkt0 at %d (%d dwords):\n", i, cnt); reg = CP_PACKET0_GET_REG(cs->packets[i]); if (CP_PACKET0_GET_ONE_REG_WR(cs->packets[i++])) { for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X -> 0x%04X\n", cs->packets[i++], reg); } } else { for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X -> 0x%04X\n", cs->packets[i++], reg); reg += 4; } } break; case PACKET_TYPE3: fprintf(file, "Pkt3 at %d :\n", i); opcode = CP_PACKET3_GET_OPCODE(cs->packets[i++]); switch (opcode) { case PACKET3_NOP: fprintf(file, " PACKET3_NOP:\n"); break; case PACKET3_3D_DRAW_VBUF: fprintf(file, " PACKET3_3D_DRAW_VBUF:\n"); break; case PACKET3_3D_DRAW_IMMD: fprintf(file, " PACKET3_3D_DRAW_IMMD:\n"); break; case PACKET3_3D_DRAW_INDX: fprintf(file, " PACKET3_3D_DRAW_INDX:\n"); break; case PACKET3_3D_LOAD_VBPNTR: fprintf(file, " PACKET3_3D_LOAD_VBPNTR:\n"); break; case PACKET3_INDX_BUFFER: fprintf(file, " PACKET3_INDX_BUFFER:\n"); break; case PACKET3_3D_DRAW_VBUF_2: fprintf(file, " PACKET3_3D_DRAW_VBUF_2:\n"); break; case PACKET3_3D_DRAW_IMMD_2: fprintf(file, " PACKET3_3D_DRAW_IMMD_2:\n"); break; case PACKET3_3D_DRAW_INDX_2: fprintf(file, " PACKET3_3D_DRAW_INDX_2:\n"); break; default: fprintf(file, "Unknow opcode 0x%02X at %d\n", opcode, i); return; } for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X\n", cs->packets[i++]); } break; case PACKET_TYPE1: case PACKET_TYPE2: default: fprintf(file, "Unknow packet 0x%08X at %d\n", cs->packets[i], i); return; } } } static struct radeon_cs_funcs radeon_cs_gem_funcs = { cs_gem_create, cs_gem_write_reloc, cs_gem_begin, cs_gem_end, cs_gem_emit, cs_gem_destroy, cs_gem_erase, cs_gem_need_flush, cs_gem_print, }; struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd) { struct radeon_cs_manager *csm; csm = (struct radeon_cs_manager*)calloc(1, sizeof(struct radeon_cs_manager)); if (csm == NULL) { return NULL; } csm->funcs = &radeon_cs_gem_funcs; csm->fd = fd; return csm; } void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm) { free(csm); } 1 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 
/* i810_drv.c -- I810 driver -*- linux-c -*-
 * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
 *	    Jeff Hartmann <jhartmann@valinux.com>
 *
 */

#include <linux/config.h>
#include "drmP.h"
#include "i810_drv.h"

#define I810_NAME	 "i810"
#define I810_DESC	 "Intel I810"
#define I810_DATE	 "20000928"
#define I810_MAJOR	 1
#define I810_MINOR	 1
#define I810_PATCHLEVEL	 0

static drm_device_t	      i810_device;
drm_ctx_t		      i810_res_ctx;

static struct file_operations i810_fops = {
#if LINUX_VERSION_CODE >= 0x020400
				/* This started being used during 2.4.0-test */
	owner:   THIS_MODULE,
#endif
	open:	 i810_open,
	flush:	 drm_flush,
	release: i810_release,
	ioctl:	 i810_ioctl,
	mmap:	 drm_mmap,
	read:	 drm_read,
	fasync:	 drm_fasync,
      	poll:	 drm_poll,
};

static struct miscdevice      i810_misc = {
	minor: MISC_DYNAMIC_MINOR,
	name:  I810_NAME,
	fops:  &i810_fops,
};

static drm_ioctl_desc_t	      i810_ioctls[] = {
	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]     = { i810_version,	  0, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)]  = { drm_getunique,  0, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]   = { drm_getmagic,	  0, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]   = { drm_irq_busid,  0, 1 },

	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)]  = { drm_setunique,  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	      = { drm_block,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]     = { drm_unblock,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]     = { i810_control,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)]  = { drm_authmagic,  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]     = { drm_addmap,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]    = { i810_addbufs,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]   = { i810_markbufs,  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]   = { i810_infobufs,  1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]   = { i810_freebufs,  1, 0 },

	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]     = { i810_addctx,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]      = { i810_rmctx,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]     = { i810_modctx,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]     = { i810_getctx,	  1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)]  = { i810_switchctx,  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]     = { i810_newctx,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]     = { i810_resctx,	  1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]    = { drm_adddraw,	  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]     = { drm_rmdraw,	  1, 1 },

	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	      = { i810_lock,	  1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]      = { i810_unlock,	  1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]      = { drm_finish,	  1, 0 },

	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]  = { drm_agp_enable,  1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]    = { drm_agp_info,    1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]   = { drm_agp_alloc,   1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]    = { drm_agp_free,    1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]    = { drm_agp_bind,    1, 1 },
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]  = { drm_agp_unbind,  1, 1 },

   	[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)]   = { i810_dma_init,   1, 1 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)]  = { i810_clear_bufs, 1, 0 },
      	[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)]  = { i810_flush_ioctl,1, 0 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage,     1, 0 },
	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf,     1, 0 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)]   = { i810_swap_bufs,  1, 0 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)]   = { i810_copybuf,    1, 0 },
   	[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy,     1, 0 },
};

#define I810_IOCTL_COUNT DRM_ARRAY_SIZE(i810_ioctls)

#ifdef MODULE
static char		      *i810 = NULL;
#endif

MODULE_AUTHOR("VA Linux Systems, Inc.");
MODULE_DESCRIPTION("Intel I810");
MODULE_PARM(i810, "s");

#ifndef MODULE
/* i810_options is called by the kernel to parse command-line options
 * passed via the boot-loader (e.g., LILO).  It calls the insmod option
 * routine, drm_parse_drm.
 */

static int __init i810_options(char *str)
{
	drm_parse_options(str);
	return 1;
}

__setup("i810=", i810_options);
#endif

static int i810_setup(drm_device_t *dev)
{
	int i;

	atomic_set(&dev->ioctl_count, 0);
	atomic_set(&dev->vma_count, 0);
	dev->buf_use	  = 0;
	atomic_set(&dev->buf_alloc, 0);

	drm_dma_setup(dev);

	atomic_set(&dev->total_open, 0);
	atomic_set(&dev->total_close, 0);
	atomic_set(&dev->total_ioctl, 0);
	atomic_set(&dev->total_irq, 0);
	atomic_set(&dev->total_ctx, 0);
	atomic_set(&dev->total_locks, 0);
	atomic_set(&dev->total_unlocks, 0);
	atomic_set(&dev->total_contends, 0);
	atomic_set(&dev->total_sleeps, 0);

	for (i = 0; i < DRM_HASH_SIZE; i++) {
		dev->magiclist[i].head = NULL;
		dev->magiclist[i].tail = NULL;
	}
	dev->maplist	    = NULL;
	dev->map_count	    = 0;
	dev->vmalist	    = NULL;
	dev->lock.hw_lock   = NULL;
	init_waitqueue_head(&dev->lock.lock_queue);
	dev->queue_count    = 0;
	dev->queue_reserved = 0;
	dev->queue_slots    = 0;
	dev->queuelist	    = NULL;
	dev->irq	    = 0;
	dev->context_flag   = 0;
	dev->interrupt_flag = 0;
	dev->dma_flag	    = 0;
	dev->last_context   = 0;
	dev->last_switch    = 0;
	dev->last_checked   = 0;
	init_timer(&dev->timer);
	init_waitqueue_head(&dev->context_wait);
#if DRM_DMA_HISTO
	memset(&dev->histo, 0, sizeof(dev->histo));
#endif
	dev->ctx_start	    = 0;
	dev->lck_start	    = 0;

	dev->buf_rp	  = dev->buf;
	dev->buf_wp	  = dev->buf;
	dev->buf_end	  = dev->buf + DRM_BSZ;
	dev->buf_async	  = NULL;
	init_waitqueue_head(&dev->buf_readers);
	init_waitqueue_head(&dev->buf_writers);

	DRM_DEBUG("\n");

	/* The kernel's context could be created here, but is now created
	   in drm_dma_enqueue.	This is more resource-efficient for
	   hardware that does not do DMA, but may mean that
	   drm_select_queue fails between the time the interrupt is
	   initialized and the time the queues are initialized. */

	return 0;
}


static int i810_takedown(drm_device_t *dev)
{
	int		  i;
	drm_magic_entry_t *pt, *next;
	drm_map_t	  *map;
	drm_vma_entry_t	  *vma, *vma_next;

	DRM_DEBUG("\n");

	if (dev->irq) i810_irq_uninstall(dev);

	down(&dev->struct_sem);
	del_timer(&dev->timer);

	if (dev->devname) {
		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
		dev->devname = NULL;
	}

	if (dev->unique) {
		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
		dev->unique = NULL;
		dev->unique_len = 0;
	}
				/* Clear pid list */
	for (i = 0; i < DRM_HASH_SIZE; i++) {
		for (pt = dev->magiclist[i].head; pt; pt = next) {
			next = pt->next;
			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
		}
		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
	}
   				/* Clear AGP information */
	if (dev->agp) {
		drm_agp_mem_t *entry;
		drm_agp_mem_t *nexte;

				/* Remove AGP resources, but leave dev->agp
                                   intact until r128_cleanup is called. */
		for (entry = dev->agp->memory; entry; entry = nexte) {
			nexte = entry->next;
			if (entry->bound) drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
		}
		dev->agp->memory = NULL;

		if (dev->agp->acquired) _drm_agp_release();

		dev->agp->acquired = 0;
		dev->agp->enabled  = 0;
	}
				/* Clear vma list (only built for debugging) */
	if (dev->vmalist) {
		for (vma = dev->vmalist; vma; vma = vma_next) {
			vma_next = vma->next;
			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
		}
		dev->vmalist = NULL;
	}

				/* Clear map area and mtrr information */
	if (dev->maplist) {
		for (i = 0; i < dev->map_count; i++) {
			map = dev->maplist[i];
			switch (map->type) {
			case _DRM_REGISTERS:
			case _DRM_FRAME_BUFFER:
#ifdef CONFIG_MTRR
				if (map->mtrr >= 0) {
					int retcode;
					retcode = mtrr_del(map->mtrr,
							   map->offset,
							   map->size);
					DRM_DEBUG("mtrr_del = %d\n", retcode);
				}
#endif
				drm_ioremapfree(map->handle, map->size);
				break;
			case _DRM_SHM:
				drm_free_pages((unsigned long)map->handle,
					       drm_order(map->size)
					       - PAGE_SHIFT,
					       DRM_MEM_SAREA);
				break;
			case _DRM_AGP:
				break;
			}
			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
		}
		drm_free(dev->maplist,
			 dev->map_count * sizeof(*dev->maplist),
			 DRM_MEM_MAPS);
		dev->maplist   = NULL;
		dev->map_count = 0;
	}

	if (dev->queuelist) {
		for (i = 0; i < dev->queue_count; i++) {
			drm_waitlist_destroy(&dev->queuelist[i]->waitlist);
			if (dev->queuelist[i]) {
				drm_free(dev->queuelist[i],
					 sizeof(*dev->queuelist[0]),
					 DRM_MEM_QUEUES);
				dev->queuelist[i] = NULL;
			}
		}
		drm_free(dev->queuelist,
			 dev->queue_slots * sizeof(*dev->queuelist),
			 DRM_MEM_QUEUES);
		dev->queuelist	 = NULL;
	}

	drm_dma_takedown(dev);

	dev->queue_count     = 0;
	if (dev->lock.hw_lock) {
		dev->lock.hw_lock    = NULL; /* SHM removed */
		dev->lock.pid	     = 0;
		wake_up_interruptible(&dev->lock.lock_queue);
	}
	up(&dev->struct_sem);

	return 0;
}

/* i810_init is called via init_module at module load time, or via
 * linux/init/main.c (this is not currently supported). */

static int __init i810_init(void)
{
	int		      retcode;
	drm_device_t	      *dev = &i810_device;

	DRM_DEBUG("\n");

	memset((void *)dev, 0, sizeof(*dev));
	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
	sema_init(&dev->struct_sem, 1);

#ifdef MODULE
	drm_parse_options(i810);
#endif
	DRM_DEBUG("doing misc_register\n");
	if ((retcode = misc_register(&i810_misc))) {
		DRM_ERROR("Cannot register \"%s\"\n", I810_NAME);
		return retcode;
	}
	dev->device = MKDEV(MISC_MAJOR, i810_misc.minor);
	dev->name   = I810_NAME;

   	DRM_DEBUG("doing mem init\n");
	drm_mem_init();
	DRM_DEBUG("doing proc init\n");
	drm_proc_init(dev);
	DRM_DEBUG("doing agp init\n");
	dev->agp    = drm_agp_init();
   	if(dev->agp == NULL) {
	   	DRM_INFO("The i810 drm module requires the agpgart module"
			 " to function correctly\nPlease load the agpgart"
			 " module before you load the i810 module\n");
	   	drm_proc_cleanup();
	   	misc_deregister(&i810_misc);
	   	i810_takedown(dev);
	   	return -ENOMEM;
	}
	DRM_DEBUG("doing ctxbitmap init\n");
	if((retcode = drm_ctxbitmap_init(dev))) {
		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
		drm_proc_cleanup();
		misc_deregister(&i810_misc);
		i810_takedown(dev);
		return retcode;
	}

	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
		 I810_NAME,
		 I810_MAJOR,
		 I810_MINOR,
		 I810_PATCHLEVEL,
		 I810_DATE,
		 i810_misc.minor);

	return 0;
}

/* i810_cleanup is called via cleanup_module at module unload time. */

static void __exit i810_cleanup(void)
{
	drm_device_t	      *dev = &i810_device;

	DRM_DEBUG("\n");

	drm_proc_cleanup();
	if (misc_deregister(&i810_misc)) {
		DRM_ERROR("Cannot unload module\n");
	} else {
		DRM_INFO("Module unloaded\n");
	}
	drm_ctxbitmap_cleanup(dev);
	i810_takedown(dev);
	if (dev->agp) {
		drm_agp_uninit();
		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
		dev->agp = NULL;
	}
}

module_init(i810_init);
module_exit(i810_cleanup);


int i810_version(struct inode *inode, struct file *filp, unsigned int cmd,
		  unsigned long arg)
{
	drm_version_t version;
	int	      len;

	if (copy_from_user(&version,
			   (drm_version_t *)arg,
			   sizeof(version)))
		return -EFAULT;

#define DRM_COPY(name,value)				     \
	len = strlen(value);				     \
	if (len > name##_len) len = name##_len;		     \
	name##_len = strlen(value);			     \
	if (len && name) {				     \
		if (copy_to_user(name, value, len))          \
			return -EFAULT;			     \
	}

	version.version_major	   = I810_MAJOR;
	version.version_minor	   = I810_MINOR;
	version.version_patchlevel = I810_PATCHLEVEL;

	DRM_COPY(version.name, I810_NAME);
	DRM_COPY(version.date, I810_DATE);
	DRM_COPY(version.desc, I810_DESC);

	if (copy_to_user((drm_version_t *)arg,
			 &version,
			 sizeof(version)))
		return -EFAULT;
	return 0;
}

int i810_open(struct inode *inode, struct file *filp)
{
	drm_device_t  *dev    = &i810_device;
	int	      retcode = 0;

	DRM_DEBUG("open_count = %d\n", dev->open_count);
	if (!(retcode = drm_open_helper(inode, filp, dev))) {
#if LINUX_VERSION_CODE < 0x020333
		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
#endif
		atomic_inc(&dev->total_open);
		spin_lock(&dev->count_lock);
		if (!dev->open_count++) {
			spin_unlock(&dev->count_lock);
			return i810_setup(dev);
		}
		spin_unlock(&dev->count_lock);
	}
	return retcode;
}

int i810_release(struct inode *inode, struct file *filp)
{
	drm_file_t    *priv   = filp->private_data;
	drm_device_t  *dev;
	int	      retcode = 0;

	lock_kernel();
	dev    = priv->dev;
	DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n",
		  current->pid, dev->device, dev->open_count);

	if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
	    && dev->lock.pid == current->pid) {
	      	i810_reclaim_buffers(dev, priv->pid);
		DRM_ERROR("Process %d dead, freeing lock for context %d\n",
			  current->pid,
			  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
		drm_lock_free(dev,
			      &dev->lock.hw_lock->lock,
			      _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));

				/* FIXME: may require heavy-handed reset of
                                   hardware at this point, possibly
                                   processed via a callback to the X
                                   server. */
	} else if (dev->lock.hw_lock) {
	   	/* The lock is required to reclaim buffers */
	   	DECLARE_WAITQUEUE(entry, current);
	   	add_wait_queue(&dev->lock.lock_queue, &entry);
		for (;;) {
			current->state = TASK_INTERRUPTIBLE;
			if (!dev->lock.hw_lock) {
				/* Device has been unregistered */
				retcode = -EINTR;
				break;
			}
			if (drm_lock_take(&dev->lock.hw_lock->lock,
					  DRM_KERNEL_CONTEXT)) {
				dev->lock.pid	    = priv->pid;
				dev->lock.lock_time = jiffies;
				atomic_inc(&dev->total_locks);
				break;	/* Got lock */
			}
				/* Contention */
			atomic_inc(&dev->total_sleeps);
			schedule();
			if (signal_pending(current)) {
				retcode = -ERESTARTSYS;
				break;
			}
		}
		current->state = TASK_RUNNING;
		remove_wait_queue(&dev->lock.lock_queue, &entry);
	   	if(!retcode) {
		   	i810_reclaim_buffers(dev, priv->pid);
		   	drm_lock_free(dev, &dev->lock.hw_lock->lock,
				      DRM_KERNEL_CONTEXT);
		}
	}
	drm_fasync(-1, filp, 0);

	down(&dev->struct_sem);
	if (priv->prev) priv->prev->next = priv->next;
	else		dev->file_first	 = priv->next;
	if (priv->next) priv->next->prev = priv->prev;