From 34797ff67c16beb9c331920f663bdf8387c14c78 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 2 Dec 2007 23:48:45 +0100 Subject: radeon_ms: radeon modesetting first commit. This should work on all radeon but there is still many things todo: - add crtc2 - tmds - lvds - add bios data table so we don't need to hardcode dac/crtc infos - separate clock control to make power saving easier & cleaner - tiling (warning tiling shouldn't be enable in double scan or interlace) - surface reg manager (this goes along with tiling) - suspend/resume hook - avivo & r500 family support - atom bios support (for posting card mostly) - finish superioctl skeleton - what else ? :) --- shared-core/radeon_ms_fence.c | 129 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 shared-core/radeon_ms_fence.c (limited to 'shared-core/radeon_ms_fence.c') diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c new file mode 100644 index 00000000..96bb0858 --- /dev/null +++ b/shared-core/radeon_ms_fence.c @@ -0,0 +1,129 @@ +/* + * Copyright 2007 Dave Airlie. + * Copyright 2007 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + * Jerome Glisse + */ +#include "radeon_ms.h" + +static void radeon_ms_fence_flush(struct drm_device *dev) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct drm_fence_class_manager *fc = &dev->fm.fence_class[0]; + uint32_t pending_flush_types = 0; + uint32_t sequence; + + if (dev_priv == NULL) { + return; + } + pending_flush_types = fc->pending_flush | + ((fc->pending_exe_flush) ? + DRM_FENCE_TYPE_EXE : 0); + if (pending_flush_types) { + sequence = mmio_read(dev_priv, dev_priv->fence_reg); + drm_fence_handler(dev, 0, sequence, pending_flush_types, 0); + } +} + +int radeon_ms_fence_emit_sequence(struct drm_device *dev, uint32_t class, + uint32_t flags, uint32_t *sequence, + uint32_t *native_type) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + uint32_t fence_id, cmd[2], i, ret; + + if (!dev_priv || !dev_priv->cp_ready) { + return -EINVAL; + } + fence_id = (++dev_priv->fence_id_last); + if (dev_priv->fence_id_last > 0x7FFFFFFF) { + fence_id = dev_priv->fence_id_last = 1; + } + *sequence = fence_id; + *native_type = DRM_FENCE_TYPE_EXE; + if (flags & DRM_RADEON_FENCE_FLAG_FLUSHED) { + *native_type |= DRM_RADEON_FENCE_TYPE_RW; + dev_priv->flush_cache(dev); + } + cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0); + cmd[1] = fence_id; + for (i = 0; i < dev_priv->usec_timeout; i++) { + ret = radeon_ms_ring_emit(dev, cmd, 2); + if (!ret) { + dev_priv->irq_emit(dev); + return 0; + } + } + return -EBUSY; +} + +void radeon_ms_fence_handler(struct drm_device * dev) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct drm_fence_manager *fm = &dev->fm; + + if (dev_priv == NULL) { + return; + } + + write_lock(&fm->lock); + radeon_ms_fence_flush(dev); + write_unlock(&fm->lock); +} + +int radeon_ms_fence_has_irq(struct drm_device *dev, uint32_t class, + uint32_t flags) +{ + /* + * We have an irq that tells us when we have a new breadcrumb. + */ + if (class == 0 && flags == DRM_FENCE_TYPE_EXE) + return 1; + + return 0; +} + +int radeon_ms_fence_types(struct drm_buffer_object *bo, + uint32_t *class, uint32_t *type) +{ + *class = 0; + if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) + *type = 3; + else + *type = 1; + return 0; +} + +void radeon_ms_poke_flush(struct drm_device *dev, uint32_t class) +{ + struct drm_fence_manager *fm = &dev->fm; + unsigned long flags; + + if (class != 0) + return; + write_lock_irqsave(&fm->lock, flags); + radeon_ms_fence_flush(dev); + write_unlock_irqrestore(&fm->lock, flags); +} -- cgit v1.2.3 From 3a51a8077bf55ba9d18805f2f03b78eb980fa982 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 6 Dec 2007 22:38:44 +0100 Subject: radeon_ms: avoid to unintialize things which haven't been initialized --- shared-core/radeon_ms_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/radeon_ms_fence.c') diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c index 96bb0858..6fcf5437 100644 --- a/shared-core/radeon_ms_fence.c +++ b/shared-core/radeon_ms_fence.c @@ -54,7 +54,7 @@ int radeon_ms_fence_emit_sequence(struct drm_device *dev, uint32_t class, struct drm_radeon_private *dev_priv = dev->dev_private; uint32_t fence_id, cmd[2], i, ret; - if (!dev_priv || !dev_priv->cp_ready) { + if (!dev_priv || dev_priv->cp_ready != 1) { return -EINVAL; } fence_id = (++dev_priv->fence_id_last); -- cgit v1.2.3 From a7dc4d08b9b4f8fe6fcaa4c778f6dd3718d1e36a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 10 Mar 2008 23:35:07 +0100 Subject: rradeon_ms: rework fence code and bring radeon ms up to date --- shared-core/radeon_ms_fence.c | 248 ++++++++++++++++++++++++++++++++---------- 1 file changed, 193 insertions(+), 55 deletions(-) (limited to 'shared-core/radeon_ms_fence.c') diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c index 6fcf5437..162d37d6 100644 --- a/shared-core/radeon_ms_fence.c +++ b/shared-core/radeon_ms_fence.c @@ -27,103 +27,241 @@ * Jerome Glisse */ #include "radeon_ms.h" +#include "amd_r3xx_fence.h" -static void radeon_ms_fence_flush(struct drm_device *dev) +#define R3XX_FENCE_SEQUENCE_RW_FLUSH 0x80000000u + +static inline int r3xx_fence_emit_sequence(struct drm_device *dev, + struct drm_radeon_private *dev_priv, + uint32_t sequence) { - struct drm_radeon_private *dev_priv = dev->dev_private; - struct drm_fence_class_manager *fc = &dev->fm.fence_class[0]; - uint32_t pending_flush_types = 0; + struct r3xx_fence *r3xx_fence = dev_priv->fence; + uint32_t cmd[2]; + int i, r; + + if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) { + r3xx_fence->sequence_last_flush = + sequence & ~R3XX_FENCE_SEQUENCE_RW_FLUSH; + /* Ask flush for VERTEX & FRAGPROG pipeline + * have 3D idle */ + dev_priv->flush_cache(dev); + } + cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0); + cmd[1] = sequence; + for (i = 0; i < dev_priv->usec_timeout; i++) { + r = radeon_ms_ring_emit(dev, cmd, 2); + if (!r) { + dev_priv->irq_emit(dev); + return 0; + } + } + return -EBUSY; +} + +static inline uint32_t r3xx_fence_sequence(struct r3xx_fence *r3xx_fence) +{ + r3xx_fence->sequence += 1; + if (unlikely(r3xx_fence->sequence > 0x7fffffffu)) { + r3xx_fence->sequence = 1; + } + return r3xx_fence->sequence; +} + +static inline void r3xx_fence_report(struct drm_device *dev, + struct drm_radeon_private *dev_priv, + struct r3xx_fence *r3xx_fence) +{ + uint32_t fence_types = DRM_FENCE_TYPE_EXE; uint32_t sequence; if (dev_priv == NULL) { return; } - pending_flush_types = fc->pending_flush | - ((fc->pending_exe_flush) ? - DRM_FENCE_TYPE_EXE : 0); - if (pending_flush_types) { - sequence = mmio_read(dev_priv, dev_priv->fence_reg); - drm_fence_handler(dev, 0, sequence, pending_flush_types, 0); + sequence = mmio_read(dev_priv, dev_priv->fence_reg); + if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) { + sequence &= ~R3XX_FENCE_SEQUENCE_RW_FLUSH; + fence_types |= DRM_RADEON_FENCE_TYPE_RW; + if (sequence == r3xx_fence->sequence_last_flush) { + r3xx_fence->sequence_last_flush = 0; + } } + /* avoid to report already reported sequence */ + if (sequence != r3xx_fence->sequence_last_reported) { + drm_fence_handler(dev, 0, sequence, fence_types, 0); + r3xx_fence->sequence_last_reported = sequence; + } +} + +static void r3xx_fence_flush(struct drm_device *dev, uint32_t class) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct r3xx_fence *r3xx_fence = dev_priv->fence; + uint32_t sequence; + + sequence = r3xx_fence_sequence(r3xx_fence); + sequence |= R3XX_FENCE_SEQUENCE_RW_FLUSH; + r3xx_fence_emit_sequence(dev, dev_priv, sequence); } -int radeon_ms_fence_emit_sequence(struct drm_device *dev, uint32_t class, - uint32_t flags, uint32_t *sequence, - uint32_t *native_type) +static void r3xx_fence_poll(struct drm_device *dev, uint32_t fence_class, + uint32_t waiting_types) { struct drm_radeon_private *dev_priv = dev->dev_private; - uint32_t fence_id, cmd[2], i, ret; + struct drm_fence_manager *fm = &dev->fm; + struct drm_fence_class_manager *fc = &fm->fence_class[fence_class]; + struct r3xx_fence *r3xx_fence = dev_priv->fence; + + if (unlikely(!dev_priv)) { + return; + } + /* if there is a RW flush pending then submit new sequence + * preceded by flush cmds */ + if (fc->pending_flush & DRM_RADEON_FENCE_TYPE_RW) { + r3xx_fence_flush(dev, 0); + fc->pending_flush &= ~DRM_RADEON_FENCE_TYPE_RW; + } + r3xx_fence_report(dev, dev_priv, r3xx_fence); + return; +} + +static int r3xx_fence_emit(struct drm_device *dev, uint32_t class, + uint32_t flags, uint32_t *sequence, + uint32_t *native_type) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct r3xx_fence *r3xx_fence = dev_priv->fence; + uint32_t tmp; if (!dev_priv || dev_priv->cp_ready != 1) { return -EINVAL; } - fence_id = (++dev_priv->fence_id_last); - if (dev_priv->fence_id_last > 0x7FFFFFFF) { - fence_id = dev_priv->fence_id_last = 1; - } - *sequence = fence_id; + *sequence = tmp = r3xx_fence_sequence(r3xx_fence); *native_type = DRM_FENCE_TYPE_EXE; if (flags & DRM_RADEON_FENCE_FLAG_FLUSHED) { *native_type |= DRM_RADEON_FENCE_TYPE_RW; - dev_priv->flush_cache(dev); + tmp |= R3XX_FENCE_SEQUENCE_RW_FLUSH; } - cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0); - cmd[1] = fence_id; - for (i = 0; i < dev_priv->usec_timeout; i++) { - ret = radeon_ms_ring_emit(dev, cmd, 2); - if (!ret) { - dev_priv->irq_emit(dev); + return r3xx_fence_emit_sequence(dev, dev_priv, tmp); +} + +static int r3xx_fence_has_irq(struct drm_device *dev, + uint32_t class, uint32_t type) +{ + const uint32_t type_irq_mask = DRM_FENCE_TYPE_EXE | + DRM_RADEON_FENCE_TYPE_RW; + /* + * We have an irq for EXE & RW fence. + */ + if (class == 0 && (type & type_irq_mask)) { + return 1; + } + return 0; +} + +static uint32_t r3xx_fence_needed_flush(struct drm_fence_object *fence) +{ + struct drm_device *dev = fence->dev; + struct drm_radeon_private *dev_priv = dev->dev_private; + struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct drm_fence_driver *driver = dev->driver->fence_driver; + uint32_t flush_types, diff; + + flush_types = fence->waiting_types & + ~(DRM_FENCE_TYPE_EXE | fence->signaled_types); + + if (flush_types == 0 || ((flush_types & ~fence->native_types) == 0)) { + return 0; + } + if (unlikely(dev_priv == NULL)) { + return 0; + } + if (r3xx_fence->sequence_last_flush) { + diff = (r3xx_fence->sequence_last_flush - fence->sequence) & + driver->sequence_mask; + if (diff < driver->wrap_diff) { return 0; } } - return -EBUSY; + return flush_types; } -void radeon_ms_fence_handler(struct drm_device * dev) +static int r3xx_fence_wait(struct drm_fence_object *fence, + int lazy, int interruptible, uint32_t mask) { - struct drm_radeon_private *dev_priv = dev->dev_private; + struct drm_device *dev = fence->dev; struct drm_fence_manager *fm = &dev->fm; + struct drm_fence_class_manager *fc = &fm->fence_class[0]; + int r; - if (dev_priv == NULL) { - return; + drm_fence_object_flush(fence, mask); + if (likely(interruptible)) { + r = wait_event_interruptible_timeout( + fc->fence_queue, + drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE), + 3 * DRM_HZ); + } else { + r = wait_event_timeout( + fc->fence_queue, + drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE), + 3 * DRM_HZ); + } + if (unlikely(r == -ERESTARTSYS)) { + return -EAGAIN; + } + if (unlikely(r == 0)) { + return -EBUSY; } - write_lock(&fm->lock); - radeon_ms_fence_flush(dev); - write_unlock(&fm->lock); -} + if (likely(mask == DRM_FENCE_TYPE_EXE || + drm_fence_object_signaled(fence, mask))) { + return 0; + } -int radeon_ms_fence_has_irq(struct drm_device *dev, uint32_t class, - uint32_t flags) -{ /* - * We have an irq that tells us when we have a new breadcrumb. + * Poll for sync flush completion. */ - if (class == 0 && flags == DRM_FENCE_TYPE_EXE) - return 1; - - return 0; + return drm_fence_wait_polling(fence, lazy, interruptible, + mask, 3 * DRM_HZ); } -int radeon_ms_fence_types(struct drm_buffer_object *bo, - uint32_t *class, uint32_t *type) +struct drm_fence_driver r3xx_fence_driver = { + .num_classes = 1, + .wrap_diff = (1 << 29), + .flush_diff = (1 << 28), + .sequence_mask = 0x7fffffffU, + .has_irq = r3xx_fence_has_irq, + .emit = r3xx_fence_emit, + .flush = r3xx_fence_flush, + .poll = r3xx_fence_poll, + .needed_flush = r3xx_fence_needed_flush, + .wait = r3xx_fence_wait, +}; + +/* this are used by the buffer object code */ +int r3xx_fence_types(struct drm_buffer_object *bo, + uint32_t *class, uint32_t *type) { *class = 0; - if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) - *type = 3; - else - *type = 1; + if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) { + *type = DRM_FENCE_TYPE_EXE | DRM_RADEON_FENCE_TYPE_RW; + } else { + *type = DRM_FENCE_TYPE_EXE; + } return 0; } -void radeon_ms_poke_flush(struct drm_device *dev, uint32_t class) +/* this are used by the irq code */ +void r3xx_fence_handler(struct drm_device * dev) { + struct drm_radeon_private *dev_priv = dev->dev_private; struct drm_fence_manager *fm = &dev->fm; - unsigned long flags; + struct drm_fence_class_manager *fc = &fm->fence_class[0]; - if (class != 0) + if (unlikely(dev_priv == NULL)) { return; - write_lock_irqsave(&fm->lock, flags); - radeon_ms_fence_flush(dev); - write_unlock_irqrestore(&fm->lock, flags); + } + + write_lock(&fm->lock); + r3xx_fence_poll(dev, 0, fc->waiting_types); + write_unlock(&fm->lock); } -- cgit v1.2.3 From 6ef119abf5d19c85fe039fd19d12e9bd64fd44df Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 20 Mar 2008 17:43:43 +0100 Subject: radeon_ms: fix fence --- shared-core/radeon_ms_fence.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'shared-core/radeon_ms_fence.c') diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c index 162d37d6..994c3e48 100644 --- a/shared-core/radeon_ms_fence.c +++ b/shared-core/radeon_ms_fence.c @@ -27,7 +27,7 @@ * Jerome Glisse */ #include "radeon_ms.h" -#include "amd_r3xx_fence.h" +#include "amd_legacy_fence.h" #define R3XX_FENCE_SEQUENCE_RW_FLUSH 0x80000000u @@ -35,7 +35,7 @@ static inline int r3xx_fence_emit_sequence(struct drm_device *dev, struct drm_radeon_private *dev_priv, uint32_t sequence) { - struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct legacy_fence *r3xx_fence = dev_priv->fence; uint32_t cmd[2]; int i, r; @@ -58,7 +58,7 @@ static inline int r3xx_fence_emit_sequence(struct drm_device *dev, return -EBUSY; } -static inline uint32_t r3xx_fence_sequence(struct r3xx_fence *r3xx_fence) +static inline uint32_t r3xx_fence_sequence(struct legacy_fence *r3xx_fence) { r3xx_fence->sequence += 1; if (unlikely(r3xx_fence->sequence > 0x7fffffffu)) { @@ -69,7 +69,7 @@ static inline uint32_t r3xx_fence_sequence(struct r3xx_fence *r3xx_fence) static inline void r3xx_fence_report(struct drm_device *dev, struct drm_radeon_private *dev_priv, - struct r3xx_fence *r3xx_fence) + struct legacy_fence *r3xx_fence) { uint32_t fence_types = DRM_FENCE_TYPE_EXE; uint32_t sequence; @@ -95,7 +95,7 @@ static inline void r3xx_fence_report(struct drm_device *dev, static void r3xx_fence_flush(struct drm_device *dev, uint32_t class) { struct drm_radeon_private *dev_priv = dev->dev_private; - struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct legacy_fence *r3xx_fence = dev_priv->fence; uint32_t sequence; sequence = r3xx_fence_sequence(r3xx_fence); @@ -109,7 +109,7 @@ static void r3xx_fence_poll(struct drm_device *dev, uint32_t fence_class, struct drm_radeon_private *dev_priv = dev->dev_private; struct drm_fence_manager *fm = &dev->fm; struct drm_fence_class_manager *fc = &fm->fence_class[fence_class]; - struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct legacy_fence *r3xx_fence = dev_priv->fence; if (unlikely(!dev_priv)) { return; @@ -129,7 +129,7 @@ static int r3xx_fence_emit(struct drm_device *dev, uint32_t class, uint32_t *native_type) { struct drm_radeon_private *dev_priv = dev->dev_private; - struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct legacy_fence *r3xx_fence = dev_priv->fence; uint32_t tmp; if (!dev_priv || dev_priv->cp_ready != 1) { @@ -162,7 +162,7 @@ static uint32_t r3xx_fence_needed_flush(struct drm_fence_object *fence) { struct drm_device *dev = fence->dev; struct drm_radeon_private *dev_priv = dev->dev_private; - struct r3xx_fence *r3xx_fence = dev_priv->fence; + struct legacy_fence *r3xx_fence = dev_priv->fence; struct drm_fence_driver *driver = dev->driver->fence_driver; uint32_t flush_types, diff; -- cgit v1.2.3 From 5891b0bd2ae441d738e78737a4c4826bd2e60b43 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 12 Apr 2008 00:15:12 +0200 Subject: radeon_ms: rework command submission ioctl & cleanup --- shared-core/radeon_ms_fence.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) (limited to 'shared-core/radeon_ms_fence.c') diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c index 994c3e48..08e53bd2 100644 --- a/shared-core/radeon_ms_fence.c +++ b/shared-core/radeon_ms_fence.c @@ -44,7 +44,10 @@ static inline int r3xx_fence_emit_sequence(struct drm_device *dev, sequence & ~R3XX_FENCE_SEQUENCE_RW_FLUSH; /* Ask flush for VERTEX & FRAGPROG pipeline * have 3D idle */ + /* FIXME: proper flush */ +#if 0 dev_priv->flush_cache(dev); +#endif } cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0); cmd[1] = sequence; @@ -78,18 +81,17 @@ static inline void r3xx_fence_report(struct drm_device *dev, return; } sequence = mmio_read(dev_priv, dev_priv->fence_reg); +DRM_INFO("%s pass fence 0x%08x\n", __func__, sequence); if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) { sequence &= ~R3XX_FENCE_SEQUENCE_RW_FLUSH; - fence_types |= DRM_RADEON_FENCE_TYPE_RW; + fence_types |= DRM_AMD_FENCE_TYPE_R; + fence_types |= DRM_AMD_FENCE_TYPE_W; if (sequence == r3xx_fence->sequence_last_flush) { r3xx_fence->sequence_last_flush = 0; } } - /* avoid to report already reported sequence */ - if (sequence != r3xx_fence->sequence_last_reported) { - drm_fence_handler(dev, 0, sequence, fence_types, 0); - r3xx_fence->sequence_last_reported = sequence; - } + drm_fence_handler(dev, 0, sequence, fence_types, 0); + r3xx_fence->sequence_last_reported = sequence; } static void r3xx_fence_flush(struct drm_device *dev, uint32_t class) @@ -116,9 +118,10 @@ static void r3xx_fence_poll(struct drm_device *dev, uint32_t fence_class, } /* if there is a RW flush pending then submit new sequence * preceded by flush cmds */ - if (fc->pending_flush & DRM_RADEON_FENCE_TYPE_RW) { + if (fc->pending_flush & (DRM_AMD_FENCE_TYPE_R | DRM_AMD_FENCE_TYPE_W)) { r3xx_fence_flush(dev, 0); - fc->pending_flush &= ~DRM_RADEON_FENCE_TYPE_RW; + fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_R; + fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_W; } r3xx_fence_report(dev, dev_priv, r3xx_fence); return; @@ -137,10 +140,12 @@ static int r3xx_fence_emit(struct drm_device *dev, uint32_t class, } *sequence = tmp = r3xx_fence_sequence(r3xx_fence); *native_type = DRM_FENCE_TYPE_EXE; - if (flags & DRM_RADEON_FENCE_FLAG_FLUSHED) { - *native_type |= DRM_RADEON_FENCE_TYPE_RW; + if (flags & DRM_AMD_FENCE_FLAG_FLUSH) { + *native_type |= DRM_AMD_FENCE_TYPE_R; + *native_type |= DRM_AMD_FENCE_TYPE_W; tmp |= R3XX_FENCE_SEQUENCE_RW_FLUSH; } +DRM_INFO("%s emit fence 0x%08x\n", __func__, tmp); return r3xx_fence_emit_sequence(dev, dev_priv, tmp); } @@ -148,7 +153,8 @@ static int r3xx_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t type) { const uint32_t type_irq_mask = DRM_FENCE_TYPE_EXE | - DRM_RADEON_FENCE_TYPE_RW; + DRM_AMD_FENCE_TYPE_R | + DRM_AMD_FENCE_TYPE_W; /* * We have an irq for EXE & RW fence. */ @@ -243,7 +249,9 @@ int r3xx_fence_types(struct drm_buffer_object *bo, { *class = 0; if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) { - *type = DRM_FENCE_TYPE_EXE | DRM_RADEON_FENCE_TYPE_RW; + *type = DRM_FENCE_TYPE_EXE | + DRM_AMD_FENCE_TYPE_R | + DRM_AMD_FENCE_TYPE_W; } else { *type = DRM_FENCE_TYPE_EXE; } -- cgit v1.2.3