From be5bf1346e49d5c2e0080913fd55e6898a8744cf Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 1 Apr 2007 16:48:38 +1000
Subject: copy over some files and reorg radeon to add ttm fencing not working
 yet

---
 shared-core/radeon_drv.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 3e56af30..9f6cff89 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -102,6 +102,11 @@
 #define DRIVER_MINOR		26
 #define DRIVER_PATCHLEVEL	0
 
+#if defined(__linux__)
+#define RADEON_HAVE_FENCE
+#define RADEON_HAVE_BUFFER
+#endif
+
 /*
  * Radeon chip families
  */
@@ -276,8 +281,8 @@ typedef struct drm_radeon_private {
 	struct mem_block *fb_heap;
 
 	/* SW interrupt */
-	wait_queue_head_t swi_queue;
-	atomic_t swi_emitted;
+	wait_queue_head_t irq_queue;
+	int counter;
 
 	struct radeon_surface surfaces[RADEON_MAX_SURFACES];
 	struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
@@ -376,6 +381,30 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
 			     drm_file_t* filp_priv,
 			     drm_radeon_kcmd_buffer_t* cmdbuf);
 
+
+#ifdef RADEON_HAVE_FENCE
+/* i915_fence.c */
+
+
+extern void radeon_fence_handler(drm_device_t *dev);
+extern int radeon_fence_emit_sequence(drm_device_t *dev, uint32_t class,
+				      uint32_t flags, uint32_t *sequence, 
+				    uint32_t *native_type);
+extern void radeon_poke_flush(drm_device_t *dev, uint32_t class);
+extern int radeon_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags);
+#endif
+
+#ifdef RADEON_HAVE_BUFFER
+/* radeon_buffer.c */
+extern drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t *dev);
+extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
+extern int radeon_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
+extern uint32_t radeon_evict_mask(drm_buffer_object_t *bo);
+extern int radeon_init_mem_type(drm_device_t * dev, uint32_t type,
+				drm_mem_type_manager_t * man);
+extern int radeon_move(drm_buffer_object_t * bo,
+		       int evict, int no_wait, drm_bo_mem_reg_t * new_mem);
+#endif
 /* Flags for stats.boxes
  */
 #define RADEON_BOX_DMA_IDLE      0x1
@@ -1184,4 +1213,19 @@ do {									\
 	write &= mask;						\
 } while (0)
 
+/* Breadcrumb - swi irq */
+#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
+
+static inline int radeon_update_breadcrumb(drm_device_t *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	dev_priv->sarea_priv->last_fence = ++dev_priv->counter;
+
+	if (dev_priv->counter > 0x7FFFFFFFUL)
+		dev_priv->sarea_priv->last_fence = dev_priv->counter = 1;
+
+	return dev_priv->counter;
+}
+
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From b1f0b2d960a8f488332652677073ab95ce72cd3f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 1 Apr 2007 18:24:23 +1000
Subject: radeon: de-static irq function, fixup fence/buffer

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 9f6cff89..6d2bcc8f 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -355,6 +355,7 @@ extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
 				/* radeon_irq.c */
 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
+extern int radeon_emit_irq(drm_device_t * dev);
 
 extern void radeon_do_release(drm_device_t * dev);
 extern int radeon_driver_vblank_wait(drm_device_t * dev,
-- 
cgit v1.2.3


From 4294dcc050c5d2685f633e8a52deb925d806be85 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@nx6125b.(none)>
Date: Tue, 5 Jun 2007 12:26:06 +1000
Subject: complete PCIE backend for ttm

ttm test runs with it at least, needs to do more testing on it
---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index c16a43eb..5a33231a 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -344,6 +344,7 @@ extern int radeon_cp_resume(DRM_IOCTL_ARGS);
 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
+extern void radeon_gart_flush(struct drm_device *dev);
 
 extern void radeon_freelist_reset(drm_device_t * dev);
 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
-- 
cgit v1.2.3


From 75c9e0d3462f04766d490fac5cc93569957a8365 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <glisse@freedesktop.org>
Date: Tue, 26 Feb 2008 23:30:45 +0100
Subject: radeon: remove TTM from an earlier merge

---
 shared-core/radeon_drv.h | 51 ++----------------------------------------------
 1 file changed, 2 insertions(+), 49 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 0c503257..1cf03415 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -104,11 +104,6 @@
 #define DRIVER_MINOR		28
 #define DRIVER_PATCHLEVEL	0
 
-#if defined(__linux__)
-#define RADEON_HAVE_FENCE
-#define RADEON_HAVE_BUFFER
-#endif
-
 /*
  * Radeon chip families
  */
@@ -296,9 +291,8 @@ typedef struct drm_radeon_private {
 	struct mem_block *fb_heap;
 
 	/* SW interrupt */
-	wait_queue_head_t irq_queue;
-	int counter;
-
+	wait_queue_head_t swi_queue;
+	atomic_t swi_emitted;
 	int vblank_crtc;
 	uint32_t irq_enable_reg;
 	int irq_enabled;
@@ -361,7 +355,6 @@ extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file
 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern void radeon_gart_flush(struct drm_device *dev);
 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
 
 extern void radeon_freelist_reset(struct drm_device * dev);
@@ -381,7 +374,6 @@ extern void radeon_mem_release(struct drm_file *file_priv,
 				/* radeon_irq.c */
 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern int radeon_emit_irq(struct drm_device * dev);
 
 extern void radeon_do_release(struct drm_device * dev);
 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
@@ -415,30 +407,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 			     struct drm_file *file_priv,
 			     drm_radeon_kcmd_buffer_t *cmdbuf);
 
-
-#ifdef RADEON_HAVE_FENCE
-/* i915_fence.c */
-
-
-extern void radeon_fence_handler(struct drm_device *dev);
-extern int radeon_fence_emit_sequence(struct drm_device *dev, uint32_t class,
-				      uint32_t flags, uint32_t *sequence, 
-				    uint32_t *native_type);
-extern void radeon_poke_flush(struct drm_device *dev, uint32_t class);
-extern int radeon_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
-#endif
-
-#ifdef RADEON_HAVE_BUFFER
-/* radeon_buffer.c */
-extern struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device *dev);
-extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
-extern int radeon_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
-extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
-extern int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
-				struct drm_mem_type_manager * man);
-extern int radeon_move(struct drm_buffer_object * bo,
-		       int evict, int no_wait, struct drm_bo_mem_reg * new_mem);
-#endif
 /* Flags for stats.boxes
  */
 #define RADEON_BOX_DMA_IDLE      0x1
@@ -1368,19 +1336,4 @@ do {									\
 	write &= mask;						\
 } while (0)
 
-/* Breadcrumb - swi irq */
-#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
-
-static inline int radeon_update_breadcrumb(struct drm_device *dev)
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-
-	dev_priv->sarea_priv->last_fence = ++dev_priv->counter;
-
-	if (dev_priv->counter > 0x7FFFFFFFUL)
-		dev_priv->sarea_priv->last_fence = dev_priv->counter = 1;
-
-	return dev_priv->counter;
-}
-
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From df9871064e8b564d9ae2e56d561b64434fd004af Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 26 Jul 2008 08:56:23 +1000
Subject: radeon: add initial atombios modesetting and GEM -> TTM translation
 layer.

This is an initial import of the atom bios parser with modesetting support
for r500 hw using atombios. It also includes a simple memory manager
layer that translates a radeon GEM style interface onto TTM internally.

So far this memory manager has only been used for pinned object allocation
for the DDX to test modesetting.
---
 shared-core/radeon_drv.h | 298 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 226 insertions(+), 72 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index e263c610..b8f49404 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -31,6 +31,7 @@
 #ifndef __RADEON_DRV_H__
 #define __RADEON_DRV_H__
 
+#include "atom.h"
 /* General customization:
  */
 
@@ -96,13 +97,13 @@
  * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
  *       new packet type)
  * 1.26- Add support for variable size PCI(E) gart aperture
- * 1.27- Add support for IGP GART
+ * 1.27- Add support for IGPGART
  * 1.28- Add support for VBL on CRTC2
  * 1.29- R500 3D cmd buffer support
  */
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		29
+#define DRIVER_MINOR		30
 #define DRIVER_PATCHLEVEL	0
 
 /*
@@ -124,23 +125,29 @@ enum radeon_family {
 	CHIP_RV380,
 	CHIP_R420,
 	CHIP_RV410,
+	CHIP_RS400,
 	CHIP_RS480,
+	CHIP_RS600,
 	CHIP_RS690,
+	CHIP_RS740,
 	CHIP_RV515,
 	CHIP_R520,
 	CHIP_RV530,
 	CHIP_RV560,
 	CHIP_RV570,
 	CHIP_R580,
+	CHIP_R600,
+	CHIP_R630,
+	CHIP_RV610,
+	CHIP_RV630,
+	CHIP_RV670,
+	CHIP_RV620,
+	CHIP_RV635,
+	CHIP_RS780,
+	CHIP_RV770,
 	CHIP_LAST,
 };
 
-enum radeon_cp_microcode_version {
-	UCODE_R100,
-	UCODE_R200,
-	UCODE_R300,
-};
-
 /*
  * Chip flags
  */
@@ -158,9 +165,42 @@ enum radeon_chip_flags {
 	RADEON_IS_IGPGART = 0x01000000UL,
 };
 
+/*
+ * Errata workarounds
+ */
+enum radeon_pll_errata {
+	CHIP_ERRATA_R300_CG             = 0x00000001,
+	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
+	CHIP_ERRATA_PLL_DELAY           = 0x00000004
+};
+
+enum radeon_ext_tmds_chip {
+	RADEON_DVOCHIP_NONE,
+	RADEON_SIL_164,
+	RADEON_SIL_1178
+};
+
+#if defined(__powerpc__)
+enum radeon_mac_model {
+	RADEON_MAC_NONE,
+	RADEON_MAC_IBOOK,
+	RADEON_MAC_POWERBOOK_EXTERNAL,
+	RADEON_MAC_POWERBOOK_INTERNAL,
+	RADEON_MAC_POWERBOOK_VGA,
+	RADEON_MAC_MINI_EXTERNAL,
+	RADEON_MAC_MINI_INTERNAL,
+	RADEON_MAC_IMAC_G5_ISIGHT
+};
+#endif
+
+
 #define GET_RING_HEAD(dev_priv)	(dev_priv->writeback_works ? \
-        DRM_READ32(  (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
-#define SET_RING_HEAD(dev_priv,val)	DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
+				 (dev_priv->mm.ring_read_ptr ? readl(dev_priv->mm.ring_read_ptr_map.virtual + 0) : DRM_READ32((dev_priv)->ring_rptr, 0 )) : \
+				 RADEON_READ(RADEON_CP_RB_RPTR))
+
+#define SET_RING_HEAD(dev_priv,val) (dev_priv->mm.ring_read_ptr ? \
+				     writel((val), dev_priv->mm.ring_read_ptr_map.virtual) : \
+				     DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)))
 
 typedef struct drm_radeon_freelist {
 	unsigned int age;
@@ -221,13 +261,35 @@ struct radeon_virt_surface {
 	struct drm_file *file_priv;
 };
 
+struct radeon_mm_info {
+	uint64_t vram_offset; // Offset into GPU space
+	uint64_t vram_size;
+	uint64_t vram_visible;
+	
+	uint64_t gart_start;
+	uint64_t gart_size;
+
+	struct drm_buffer_object *pcie_table;
+	struct drm_bo_kmap_obj pcie_table_map;
+
+	struct drm_buffer_object *ring;
+	struct drm_bo_kmap_obj ring_map;
+
+	struct drm_buffer_object *ring_read_ptr;
+	struct drm_bo_kmap_obj ring_read_ptr_map;
+};
+
+#include "radeon_mode.h"
+
+struct drm_radeon_master_private {
+	drm_local_map_t *sarea;
+	drm_radeon_sarea_t *sarea_priv;
+};
+
 typedef struct drm_radeon_private {
 
 	drm_radeon_ring_buffer_t ring;
-	drm_radeon_sarea_t *sarea_priv;
 
-	u32 fb_location;
-	u32 fb_size;
 	int new_memmap;
 
 	int gart_size;
@@ -245,8 +307,6 @@ typedef struct drm_radeon_private {
 
 	int usec_timeout;
 
-	int microcode_version;
-
 	struct {
 		u32 boxes;
 		int freelist_timeouts;
@@ -282,8 +342,6 @@ typedef struct drm_radeon_private {
 	unsigned long buffers_offset;
 	unsigned long gart_textures_offset;
 
-	drm_local_map_t *sarea;
-	drm_local_map_t *mmio;
 	drm_local_map_t *cp_ring;
 	drm_local_map_t *ring_rptr;
 	drm_local_map_t *gart_textures;
@@ -292,8 +350,8 @@ typedef struct drm_radeon_private {
 	struct mem_block *fb_heap;
 
 	/* SW interrupt */
+	int counter;
 	wait_queue_head_t swi_queue;
-	atomic_t swi_emitted;
 	int vblank_crtc;
 	uint32_t irq_enable_reg;
 	int irq_enabled;
@@ -302,9 +360,6 @@ typedef struct drm_radeon_private {
 	struct radeon_surface surfaces[RADEON_MAX_SURFACES];
 	struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
 
-	unsigned long pcigart_offset;
-	unsigned int pcigart_offset_set;
-	struct drm_ati_pcigart_info gart_info;
 
 	u32 scratch_ages[5];
 
@@ -316,6 +371,28 @@ typedef struct drm_radeon_private {
 	unsigned long fb_aper_offset;
 
 	int num_gb_pipes;
+
+	struct radeon_mm_info mm;
+	drm_local_map_t *mmio;
+
+	uint32_t chip_family;
+
+	unsigned long pcigart_offset;
+	unsigned int pcigart_offset_set;
+	struct drm_ati_pcigart_info gart_info;
+
+	struct radeon_mode_info mode_info;
+
+	uint8_t *bios; /* copy of the BIOS image */
+	bool is_atom_bios;
+	uint16_t bios_header_start;
+	u32 fb_location;
+	u32 fb_size;
+	bool is_ddr;
+	u32 ram_width;
+
+	enum radeon_pll_errata pll_errata;
+	
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -330,6 +407,7 @@ typedef struct drm_radeon_kcmd_buffer {
 } drm_radeon_kcmd_buffer_t;
 
 extern int radeon_no_wb;
+extern int radeon_dynclks;
 extern struct drm_ioctl_desc radeon_ioctls[];
 extern int radeon_max_ioctl;
 
@@ -417,9 +495,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_BOX_WAIT_IDLE     0x8
 #define RADEON_BOX_TEXTURE_LOAD  0x10
 
+#define R600_CONFIG_MEMSIZE                                     0x5428
+#define R600_CONFIG_APER_SIZE                                   0x5430
 /* Register definitions, register access macros and drmAddMap constants
  * for Radeon kernel driver.
  */
+
+#include "radeon_reg.h"
+
 #define RADEON_AGP_COMMAND		0x0f60
 #define RADEON_AGP_COMMAND_PCI_CONFIG	0x0060	/* offset in PCI config */
 #       define RADEON_AGP_ENABLE            (1<<8)
@@ -522,16 +605,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define R520_MC_IND_WR_EN (1 << 24)
 #define R520_MC_IND_DATA  0x74
 
-#define RV515_MC_FB_LOCATION 0x01
-#define RV515_MC_AGP_LOCATION 0x02
-#define RV515_MC_AGP_BASE     0x03
-#define RV515_MC_AGP_BASE_2   0x04
-
-#define R520_MC_FB_LOCATION 0x04
-#define R520_MC_AGP_LOCATION 0x05
-#define R520_MC_AGP_BASE     0x06
-#define R520_MC_AGP_BASE_2   0x07
-
 #define RADEON_MPP_TB_CONFIG		0x01c0
 #define RADEON_MEM_CNTL			0x0140
 #define RADEON_MEM_SDRAM_MODE_REG	0x0158
@@ -601,9 +674,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define RADEON_SCRATCHOFF( x )		(RADEON_SCRATCH_REG_OFFSET + 4*(x))
 
-#define GET_SCRATCH( x )	(dev_priv->writeback_works			\
-				? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
-				: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
+#define GET_SCRATCH( x )	(dev_priv->writeback_works ?			\
+				 (dev_priv->mm.ring_read_ptr ? \
+				  readl(dev_priv->mm.ring_read_ptr_map.virtual + RADEON_SCRATCHOFF(0)) : \
+				  DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
+				 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
 
 #define RADEON_CRTC_CRNT_FRAME 0x0214
 #define RADEON_CRTC2_CRNT_FRAME 0x0314
@@ -628,11 +703,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define RADEON_SW_INT_FIRE		(1 << 26)
 #       define R500_DISPLAY_INT_STATUS          (1 << 0)
 
+#define RADEON_HOST_PATH_CNTL               0x0130
+#       define RADEON_HDP_SOFT_RESET        (1 << 26)
+#       define RADEON_HDP_APER_CNTL         (1 << 23)
 
-#define RADEON_HOST_PATH_CNTL		0x0130
-#	define RADEON_HDP_SOFT_RESET		(1 << 26)
-#	define RADEON_HDP_WC_TIMEOUT_MASK	(7 << 28)
-#	define RADEON_HDP_WC_TIMEOUT_28BCLK	(7 << 28)
+#define RADEON_NB_TOM                       0x15c
 
 #define RADEON_ISYNC_CNTL		0x1724
 #	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)
@@ -703,11 +778,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define R300_ZC_FREE		        (1 << 1)
 #	define R300_ZC_FLUSH_ALL		0x3
 #	define R300_ZC_BUSY		        (1 << 31)
-#define RADEON_RB3D_DSTCACHE_CTLSTAT            0x325c
-#	define RADEON_RB3D_DC_FLUSH		(3 << 0)
-#	define RADEON_RB3D_DC_FREE		(3 << 2)
-#	define RADEON_RB3D_DC_FLUSH_ALL		0xf
-#	define RADEON_RB3D_DC_BUSY		(1 << 31)
 #define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
 #	define R300_RB3D_DC_FINISH		(1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
@@ -981,27 +1051,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_NUM_VERTICES_SHIFT		16
 
 #define RADEON_COLOR_FORMAT_CI8		2
-#define RADEON_COLOR_FORMAT_ARGB1555	3
-#define RADEON_COLOR_FORMAT_RGB565	4
-#define RADEON_COLOR_FORMAT_ARGB8888	6
-#define RADEON_COLOR_FORMAT_RGB332	7
-#define RADEON_COLOR_FORMAT_RGB8	9
-#define RADEON_COLOR_FORMAT_ARGB4444	15
-
-#define RADEON_TXFORMAT_I8		0
-#define RADEON_TXFORMAT_AI88		1
-#define RADEON_TXFORMAT_RGB332		2
-#define RADEON_TXFORMAT_ARGB1555	3
-#define RADEON_TXFORMAT_RGB565		4
-#define RADEON_TXFORMAT_ARGB4444	5
-#define RADEON_TXFORMAT_ARGB8888	6
-#define RADEON_TXFORMAT_RGBA8888	7
-#define RADEON_TXFORMAT_Y8		8
-#define RADEON_TXFORMAT_VYUY422         10
-#define RADEON_TXFORMAT_YVYU422         11
-#define RADEON_TXFORMAT_DXT1            12
-#define RADEON_TXFORMAT_DXT23           14
-#define RADEON_TXFORMAT_DXT45           15
 
 #define R200_PP_TXCBLEND_0                0x2f00
 #define R200_PP_TXCBLEND_1                0x2f10
@@ -1187,18 +1236,16 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_RING_HIGH_MARK		128
 
 #define RADEON_PCIGART_TABLE_SIZE      (32*1024)
+#define RADEON_DEFAULT_RING_SIZE       (1024*1024)
+#define RADEON_DEFAULT_CP_TIMEOUT     100000  /* usecs */
 
 #define RADEON_READ(reg)    DRM_READ32(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE(reg,val)  DRM_WRITE32( dev_priv->mmio, (reg), (val) )
 #define RADEON_READ8(reg)	DRM_READ8(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE8(reg,val)	DRM_WRITE8( dev_priv->mmio, (reg), (val) )
 
-#define RADEON_WRITE_PLL( addr, val )					\
-do {									\
-	RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,				\
-		       ((addr) & 0x1f) | RADEON_PLL_WR_EN );		\
-	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
-} while (0)
+extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
+extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
 
 #define RADEON_WRITE_PCIE( addr, val )					\
 do {									\
@@ -1311,7 +1358,7 @@ do {									\
 	        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
 	        OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );			\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
+	        OUT_RING( CP_PACKET0( R300_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
 	        OUT_RING( R300_ZC_FLUSH_ALL );				\
         }                                                               \
 } while (0)
@@ -1333,7 +1380,8 @@ do {									\
 
 #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
+	struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;		\
+	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;		\
 	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
 		int __ret = radeon_do_cp_idle( dev_priv );		\
 		if ( __ret ) return __ret;				\
@@ -1439,4 +1487,110 @@ do {									\
 	write &= mask;						\
 } while (0)
 
+/* radeon GEM->TTM munger */
+struct drm_radeon_gem_object {
+	/* wrap a TTM bo */
+	struct drm_buffer_object *bo;
+	struct drm_fence_object *fence;
+	struct drm_gem_object *obj;
+	
+};
+
+extern int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
+				 struct drm_file *file_priv);
+
+extern int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
+				   struct drm_file *file_priv);
+
+extern int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+				   struct drm_file *file_priv);
+
+extern int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
+				 struct drm_file *file_priv);
+extern int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
+				   struct drm_file *file_priv);
+
+extern void radeon_fence_handler(struct drm_device *dev);
+extern int radeon_fence_emit_sequence(struct drm_device *dev, uint32_t class,
+				      uint32_t flags, uint32_t *sequence, 
+				    uint32_t *native_type);
+extern void radeon_poke_flush(struct drm_device *dev, uint32_t class);
+extern int radeon_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
+
+/* radeon_buffer.c */
+extern struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device *dev);
+extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
+extern int radeon_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
+extern int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
+				struct drm_mem_type_manager * man);
+extern int radeon_move(struct drm_buffer_object * bo,
+		       int evict, int no_wait, struct drm_bo_mem_reg * new_mem);
+
+extern void radeon_gart_flush(struct drm_device *dev);
+extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
+
+#define BREADCRUMB_BITS 31
+#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
+
+/* Breadcrumb - swi irq */
+#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
+
+static inline int radeon_update_breadcrumb(struct drm_device *dev)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct drm_radeon_master_private *master_priv;
+
+	++dev_priv->counter;
+	if (dev_priv->counter > BREADCRUMB_MASK)
+		dev_priv->counter = 1;
+
+	if (dev->primary->master) {
+		master_priv = dev->primary->master->driver_priv;
+		       
+		if (master_priv->sarea_priv)
+			master_priv->sarea_priv->last_fence = dev_priv->counter;
+	}
+	return dev_priv->counter;
+}
+
+#define radeon_is_avivo(dev_priv) ((dev_priv->chip_family >= CHIP_RS600))
+
+#define radeon_is_dce3(dev_priv) ((dev_priv->chip_family >= CHIP_RV620))
+
+#define radeon_bios8(dev_priv, v) (dev_priv->bios[v])
+#define radeon_bios16(dev_priv, v) (dev_priv->bios[v] | (dev_priv->bios[(v) + 1] << 8))
+#define radeon_bios32(dev_priv, v) ((dev_priv->bios[v]) | \
+				    (dev_priv->bios[(v) + 1] << 8) | \
+				    (dev_priv->bios[(v) + 2] << 16) | \
+				    (dev_priv->bios[(v) + 3] << 24))
+
+extern int radeon_emit_irq(struct drm_device * dev);
+
+extern void radeon_gem_free_object(struct drm_gem_object *obj);
+extern int radeon_gem_init_object(struct drm_gem_object *obj);
+extern int radeon_gem_mm_init(struct drm_device *dev);
+extern void radeon_gem_mm_fini(struct drm_device *dev);
+extern int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
+				struct drm_file *file_priv);
+extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
+				  struct drm_file *file_priv);
+int radeon_gem_object_pin(struct drm_gem_object *obj,
+			  uint32_t alignment);
+int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv);
+int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
+				struct drm_file *file_priv);
+struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
+					       int initial_domain);
+int radeon_modeset_init(struct drm_device *dev);
+void radeon_modeset_cleanup(struct drm_device *dev);
+extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr);
+extern void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val);
+
+extern void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on);
+#define RADEONFB_CONN_LIMIT 4
+
+extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
+extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
+extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From 38835f9cd2b44cfb6587a52ba1bfe292b958d0e1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 28 Jul 2008 15:21:13 +1000
Subject: radeon command submission start

take code from Jerome munge into a TTM IB re-use
---
 shared-core/radeon_drv.h | 56 +++++++++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 15 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index b8f49404..c431fe4a 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -195,11 +195,11 @@ enum radeon_mac_model {
 
 
 #define GET_RING_HEAD(dev_priv)	(dev_priv->writeback_works ? \
-				 (dev_priv->mm.ring_read_ptr ? readl(dev_priv->mm.ring_read_ptr_map.virtual + 0) : DRM_READ32((dev_priv)->ring_rptr, 0 )) : \
+				 (dev_priv->mm.ring_read.bo ? readl(dev_priv->mm.ring_read.kmap.virtual + 0) : DRM_READ32((dev_priv)->ring_rptr, 0 )) : \
 				 RADEON_READ(RADEON_CP_RB_RPTR))
 
-#define SET_RING_HEAD(dev_priv,val) (dev_priv->mm.ring_read_ptr ? \
-				     writel((val), dev_priv->mm.ring_read_ptr_map.virtual) : \
+#define SET_RING_HEAD(dev_priv,val) (dev_priv->mm.ring_read.bo ? \
+				     writel((val), dev_priv->mm.ring_read.kmap.virtual) : \
 				     DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)))
 
 typedef struct drm_radeon_freelist {
@@ -261,6 +261,11 @@ struct radeon_virt_surface {
 	struct drm_file *file_priv;
 };
 
+struct radeon_mm_obj {
+	struct drm_buffer_object *bo;
+	struct drm_bo_kmap_obj kmap;
+};
+
 struct radeon_mm_info {
 	uint64_t vram_offset; // Offset into GPU space
 	uint64_t vram_size;
@@ -268,15 +273,10 @@ struct radeon_mm_info {
 	
 	uint64_t gart_start;
 	uint64_t gart_size;
-
-	struct drm_buffer_object *pcie_table;
-	struct drm_bo_kmap_obj pcie_table_map;
-
-	struct drm_buffer_object *ring;
-	struct drm_bo_kmap_obj ring_map;
-
-	struct drm_buffer_object *ring_read_ptr;
-	struct drm_bo_kmap_obj ring_read_ptr_map;
+	
+	struct radeon_mm_obj pcie_table;
+	struct radeon_mm_obj ring;
+	struct radeon_mm_obj ring_read;
 };
 
 #include "radeon_mode.h"
@@ -286,6 +286,25 @@ struct drm_radeon_master_private {
 	drm_radeon_sarea_t *sarea_priv;
 };
 
+/* command submission struct */
+struct drm_radeon_cs_priv {
+	uint32_t id_wcnt;
+	uint32_t id_scnt;
+	uint32_t id_last_wcnt;
+	uint32_t id_last_scnt;
+
+	int (*parse)(struct drm_device *dev, void *ib,
+			uint32_t *packets, uint32_t dwords);
+	void (*id_emit)(struct drm_device *dev, uint32_t *id);
+	uint32_t (*id_last_get)(struct drm_device *dev);
+	/* this ib handling callback are for hidding memory manager drm
+	 * from memory manager less drm, free have to emit ib discard
+	 * sequence into the ring */
+	int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords);
+	uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
+	void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
+};
+
 typedef struct drm_radeon_private {
 
 	drm_radeon_ring_buffer_t ring;
@@ -392,7 +411,11 @@ typedef struct drm_radeon_private {
 	u32 ram_width;
 
 	enum radeon_pll_errata pll_errata;
-	
+
+	struct radeon_mm_obj **ib_objs;
+	/* ib bitmap */
+	uint64_t ib_alloc_bitmap; // TO DO replace with a real bitmap
+	struct drm_radeon_cs_priv cs;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -669,14 +692,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_SCRATCH_REG3		0x15ec
 #define RADEON_SCRATCH_REG4		0x15f0
 #define RADEON_SCRATCH_REG5		0x15f4
+#define RADEON_SCRATCH_REG6		0x15f8
 #define RADEON_SCRATCH_UMSK		0x0770
 #define RADEON_SCRATCH_ADDR		0x0774
 
 #define RADEON_SCRATCHOFF( x )		(RADEON_SCRATCH_REG_OFFSET + 4*(x))
 
 #define GET_SCRATCH( x )	(dev_priv->writeback_works ?			\
-				 (dev_priv->mm.ring_read_ptr ? \
-				  readl(dev_priv->mm.ring_read_ptr_map.virtual + RADEON_SCRATCHOFF(0)) : \
+				 (dev_priv->mm.ring_read.bo ? \
+				  readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(0)) : \
 				  DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
 				 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
 
@@ -1593,4 +1617,6 @@ extern void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on);
 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
+extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
+extern int radeon_cs_init(struct drm_device *dev);
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From dc3a7c023dd089150ee2dc40755fde348252bedb Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 28 Jul 2008 17:27:24 +1000
Subject: r300: initial command stream parser for packet 0.

this at least parses the DDX stream and lets me run gnome-terminal/metacity
---
 shared-core/radeon_drv.h | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index c431fe4a..232102d5 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1619,4 +1619,11 @@ extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *mas
 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
 extern int radeon_cs_init(struct drm_device *dev);
+
+#define MARK_SAFE		1
+#define MARK_CHECK_OFFSET	2
+#define MARK_CHECK_SCISSOR	3
+
+extern int r300_check_range(unsigned reg, int count);
+extern int r300_get_reg_flags(unsigned reg);
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From 4234f82acc70f41e005d8cc301da56634352425c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 29 Jul 2008 16:51:47 +1000
Subject: radeon_cs: add relocate hook for mm and non-mm relocations

---
 shared-core/radeon_drv.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 232102d5..f79eade5 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -293,8 +293,8 @@ struct drm_radeon_cs_priv {
 	uint32_t id_last_wcnt;
 	uint32_t id_last_scnt;
 
-	int (*parse)(struct drm_device *dev, void *ib,
-			uint32_t *packets, uint32_t dwords);
+	int (*parse)(struct drm_device *dev, struct drm_file *file_priv,
+		     void *ib, uint32_t *packets, uint32_t dwords);
 	void (*id_emit)(struct drm_device *dev, uint32_t *id);
 	uint32_t (*id_last_get)(struct drm_device *dev);
 	/* this ib handling callback are for hidding memory manager drm
@@ -303,6 +303,9 @@ struct drm_radeon_cs_priv {
 	int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords);
 	uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
 	void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
+	/* do a relocation either MM or non-MM */
+	bool (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
+			 uint32_t *reloc, uint32_t *offset);
 };
 
 typedef struct drm_radeon_private {
@@ -391,6 +394,7 @@ typedef struct drm_radeon_private {
 
 	int num_gb_pipes;
 
+	int mm_disabled; /* on OSes with no MM this will be 1*/
 	struct radeon_mm_info mm;
 	drm_local_map_t *mmio;
 
-- 
cgit v1.2.3


From 0452be882607f2d1601f4e592a11ccf543f5f9ca Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 29 Jul 2008 18:05:11 +1000
Subject: radeon: move code around putting emit into cs

---
 shared-core/radeon_drv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index f79eade5..e55a9697 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -300,11 +300,11 @@ struct drm_radeon_cs_priv {
 	/* this ib handling callback are for hidding memory manager drm
 	 * from memory manager less drm, free have to emit ib discard
 	 * sequence into the ring */
-	int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords);
+	int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords, uint32_t *card_offset);
 	uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
 	void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
 	/* do a relocation either MM or non-MM */
-	bool (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
+	int (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
 			 uint32_t *reloc, uint32_t *offset);
 };
 
-- 
cgit v1.2.3


From aa8e15f8b51e555e78cb93e279bad5843eea5391 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 4 Aug 2008 14:59:17 +1000
Subject: radeon: add userspace mm enable switch

---
 shared-core/radeon_drv.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index e55a9697..0363dfd4 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -314,6 +314,8 @@ typedef struct drm_radeon_private {
 
 	int new_memmap;
 
+	bool user_mm_enable;
+
 	int gart_size;
 	u32 gart_vm_start;
 	unsigned long gart_buffers_offset;
-- 
cgit v1.2.3


From 513d4c3ff1937159e0d32047376415df09031ce6 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 6 Aug 2008 10:21:20 +1000
Subject: radeon: fix setting new memmap in right place

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 0363dfd4..94975e4d 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -312,7 +312,7 @@ typedef struct drm_radeon_private {
 
 	drm_radeon_ring_buffer_t ring;
 
-	int new_memmap;
+	bool new_memmap;
 
 	bool user_mm_enable;
 
-- 
cgit v1.2.3


From c2184e450e4c5613c1f1a004d183ad478358013e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 8 Aug 2008 16:04:45 +1000
Subject: radeon: add initial support for legacy crtc/encoders.

not all there yet
---
 shared-core/radeon_drv.h | 106 +++++++++++++++++++++++++++++++----------------
 1 file changed, 71 insertions(+), 35 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 94975e4d..51a5b00c 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1277,41 +1277,59 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
 
-#define RADEON_WRITE_PCIE( addr, val )					\
+#define RADEON_WRITE_P(reg, val, mask)		\
+do {						\
+	uint32_t tmp = RADEON_READ(reg);	\
+	tmp &= ~(mask);				\
+	tmp |= ((val) & ~(mask));		\
+	RADEON_WRITE(reg, tmp);			\
+} while(0)
+
+#define RADEON_WRITE_PLL_P(dev_priv, addr, val, mask)		\
+do {								\
+	uint32_t tmp_ = RADEON_READ_PLL(dev_priv, addr);	\
+	tmp_ &= (mask);						\
+	tmp_ |= ((val) & ~(mask));				\
+	RADEON_WRITE_PLL(dev_priv, addr, tmp_);			\
+} while (0)
+
+
+
+#define RADEON_WRITE_PCIE(addr, val)					\
 do {									\
-	RADEON_WRITE8( RADEON_PCIE_INDEX,				\
+	RADEON_WRITE8(RADEON_PCIE_INDEX,				\
 			((addr) & 0xff));				\
-	RADEON_WRITE( RADEON_PCIE_DATA, (val) );			\
+	RADEON_WRITE(RADEON_PCIE_DATA, (val));			\
 } while (0)
 
-#define R500_WRITE_MCIND( addr, val )					\
+#define R500_WRITE_MCIND(addr, val)					\
 do {								\
 	RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));	\
 	RADEON_WRITE(R520_MC_IND_DATA, (val));			\
 	RADEON_WRITE(R520_MC_IND_INDEX, 0);	\
 } while (0)
 
-#define RS480_WRITE_MCIND( addr, val )				\
+#define RS480_WRITE_MCIND(addr, val)				\
 do {									\
-	RADEON_WRITE( RS480_NB_MC_INDEX,				\
+	RADEON_WRITE(RS480_NB_MC_INDEX,				\
 			((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);	\
-	RADEON_WRITE( RS480_NB_MC_DATA, (val) );			\
-	RADEON_WRITE( RS480_NB_MC_INDEX, 0xff );			\
+	RADEON_WRITE(RS480_NB_MC_DATA, (val));			\
+	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);			\
 } while (0)
 
-#define RS690_WRITE_MCIND( addr, val )					\
+#define RS690_WRITE_MCIND(addr, val)					\
 do {								\
 	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));	\
 	RADEON_WRITE(RS690_MC_DATA, val);			\
 	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);	\
 } while (0)
 
-#define IGP_WRITE_MCIND( addr, val )				\
+#define IGP_WRITE_MCIND(addr, val)				\
 do {									\
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
-	        RS690_WRITE_MCIND( addr, val );                         \
-	else                                                            \
-	        RS480_WRITE_MCIND( addr, val );                         \
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
+		RS690_WRITE_MCIND(addr, val);				\
+	else								\
+		RS480_WRITE_MCIND(addr, val);				\
 } while (0)
 
 #define CP_PACKET0( reg, n )						\
@@ -1355,42 +1373,42 @@ do {									\
 
 #define RADEON_FLUSH_CACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH);				\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH );			\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);			\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );			\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);			\
+	}                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_ZC_FLUSH );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH);				\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) );	\
-	        OUT_RING( R300_ZC_FLUSH );				\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);			\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( R300_ZC_FLUSH_ALL );				\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH_ALL);				\
+	}                                                               \
 } while (0)
 
 /* ================================================================
@@ -1411,7 +1429,7 @@ do {									\
 #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
 	struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;		\
-	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;		\
+	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;	\
 	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
 		int __ret = radeon_do_cp_idle( dev_priv );		\
 		if ( __ret ) return __ret;				\
@@ -1587,6 +1605,23 @@ static inline int radeon_update_breadcrumb(struct drm_device *dev)
 
 #define radeon_is_dce3(dev_priv) ((dev_priv->chip_family >= CHIP_RV620))
 
+#define radeon_is_rv100(dev_priv) ((dev_priv->chip_family == CHIP_RV100) || \
+				   (dev_priv->chip_family == CHIP_RV200) || \
+				   (dev_priv->chip_family == CHIP_RS100) || \
+				   (dev_priv->chip_family == CHIP_RS200) || \
+				   (dev_priv->chip_family == CHIP_RV250) || \
+				   (dev_priv->chip_family == CHIP_RV280) || \
+				   (dev_priv->chip_family == CHIP_RS300))
+
+#define radeon_is_r300(dev_priv) ((dev_priv->chip_family == CHIP_R300)  || \
+				  (dev_priv->chip_family == CHIP_RV350) || \
+				  (dev_priv->chip_family == CHIP_R350)  || \
+				  (dev_priv->chip_family == CHIP_RV380) || \
+				  (dev_priv->chip_family == CHIP_R420)  || \
+				  (dev_priv->chip_family == CHIP_RV410) || \
+				  (dev_priv->chip_family == CHIP_RS400) || \
+				  (dev_priv->chip_family == CHIP_RS480))
+
 #define radeon_bios8(dev_priv, v) (dev_priv->bios[v])
 #define radeon_bios16(dev_priv, v) (dev_priv->bios[v] | (dev_priv->bios[(v) + 1] << 8))
 #define radeon_bios32(dev_priv, v) ((dev_priv->bios[v]) | \
@@ -1594,6 +1629,7 @@ static inline int radeon_update_breadcrumb(struct drm_device *dev)
 				    (dev_priv->bios[(v) + 2] << 16) | \
 				    (dev_priv->bios[(v) + 3] << 24))
 
+extern void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv);
 extern int radeon_emit_irq(struct drm_device * dev);
 
 extern void radeon_gem_free_object(struct drm_gem_object *obj);
-- 
cgit v1.2.3


From 957c71ff52e93bb2c1bc01b99d29d763d0ef3899 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 14 Aug 2008 09:10:11 +1000
Subject: radeon: FEDORA: add old DMA buffers on top of GEM

This really shouldn't go upstream, it just lets me
run the old 3D driver on GEM setup system
---
 shared-core/radeon_drv.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 51a5b00c..138db794 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -277,6 +277,9 @@ struct radeon_mm_info {
 	struct radeon_mm_obj pcie_table;
 	struct radeon_mm_obj ring;
 	struct radeon_mm_obj ring_read;
+
+	struct radeon_mm_obj dma_bufs;
+	struct drm_map fake_agp_map;
 };
 
 #include "radeon_mode.h"
-- 
cgit v1.2.3


From 18020e5e9647e218caf8f1566cdc053aac126f23 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 14 Aug 2008 09:12:36 +1000
Subject: radeon: make buffer swap for older drivers work again on GEM

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 138db794..aa5b4ba8 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1664,6 +1664,7 @@ extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *mas
 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
 extern int radeon_cs_init(struct drm_device *dev);
+void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
 
 #define MARK_SAFE		1
 #define MARK_CHECK_OFFSET	2
-- 
cgit v1.2.3


From b0ee12e6bb55655c92184483a065780529c8aa63 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 14 Aug 2008 09:14:14 +1000
Subject: radeon: use mm_enabled variable to denote memory manager running

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index aa5b4ba8..df08b8d3 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -399,7 +399,7 @@ typedef struct drm_radeon_private {
 
 	int num_gb_pipes;
 
-	int mm_disabled; /* on OSes with no MM this will be 1*/
+	bool mm_enabled;
 	struct radeon_mm_info mm;
 	drm_local_map_t *mmio;
 
-- 
cgit v1.2.3


From 5f427e9aaed76ec827b9523b4022205f5bd09a4a Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 11 Aug 2008 12:29:42 -0400
Subject: Brute force port of legacy crtc/encoder code

- removed save/init/restore chain with set functions
---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index df08b8d3..fb266093 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1277,7 +1277,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_READ8(reg)	DRM_READ8(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE8(reg,val)	DRM_WRITE8( dev_priv->mmio, (reg), (val) )
 
-extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
+extern u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
 
 #define RADEON_WRITE_P(reg, val, mask)		\
-- 
cgit v1.2.3


From b486ed7f7d89528c94f2345040324946f6eadc81 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 12 Aug 2008 13:52:35 -0400
Subject: Get legacy working finally

- extra ~ in RADEON_WRITE_P()
- re-arrange crtc setup a bit
- add debugging for tracing calls
- fix pitch calculation
---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index fb266093..2b8d7f6e 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1283,7 +1283,7 @@ extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint
 #define RADEON_WRITE_P(reg, val, mask)		\
 do {						\
 	uint32_t tmp = RADEON_READ(reg);	\
-	tmp &= ~(mask);				\
+	tmp &= (mask);				\
 	tmp |= ((val) & ~(mask));		\
 	RADEON_WRITE(reg, tmp);			\
 } while(0)
-- 
cgit v1.2.3


From 30ff279e42b3b0608e8ff6620d2958c174449798 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 14 Aug 2008 14:43:51 +1000
Subject: radeon: add support for memory map init

---
 shared-core/radeon_drv.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index a40ff6dd..9edd3884 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -418,6 +418,10 @@ typedef struct drm_radeon_private {
 	bool is_ddr;
 	u32 ram_width;
 
+	uint32_t mc_fb_location;
+	uint32_t mc_agp_loc_lo;
+	uint32_t mc_agp_loc_hi;
+
 	enum radeon_pll_errata pll_errata;
 	
 	int num_gb_pipes;
@@ -1655,7 +1659,8 @@ int radeon_modeset_init(struct drm_device *dev);
 void radeon_modeset_cleanup(struct drm_device *dev);
 extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr);
 extern void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val);
-
+void radeon_read_agp_location(drm_radeon_private_t *dev_priv, u32 *agp_lo, u32 *agp_hi);
+void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc);
 extern void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on);
 #define RADEONFB_CONN_LIMIT 4
 
-- 
cgit v1.2.3


From 2d4cf9cc0f31ca316b109cceffc463ea52db92f2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 19 Aug 2008 08:18:46 +1000
Subject: radeon: oops set correct scratch

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 9edd3884..019491c7 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -717,7 +717,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define GET_SCRATCH( x )	(dev_priv->writeback_works ?			\
 				 (dev_priv->mm.ring_read.bo ? \
-				  readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(0)) : \
+				  readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(x)) : \
 				  DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
 				 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
 
-- 
cgit v1.2.3


From 2a6dad31d84252d505f392f91dffd90689bb947c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 18 Sep 2008 10:05:59 +1000
Subject: radeon: add initial suspend/resume support

plus a bunch of fixes
---
 shared-core/radeon_drv.h | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 019491c7..662d9cc3 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -273,6 +273,8 @@ struct radeon_mm_info {
 	
 	uint64_t gart_start;
 	uint64_t gart_size;
+
+	void *pcie_table_backup;
 	
 	struct radeon_mm_obj pcie_table;
 	struct radeon_mm_obj ring;
@@ -314,6 +316,11 @@ struct drm_radeon_cs_priv {
 			 uint32_t *reloc, uint32_t *offset);
 };
 
+struct radeon_pm_regs {
+	uint32_t crtc_ext_cntl;
+	uint32_t bios_scratch[8];
+};
+
 typedef struct drm_radeon_private {
 
 	drm_radeon_ring_buffer_t ring;
@@ -432,6 +439,8 @@ typedef struct drm_radeon_private {
 	/* ib bitmap */
 	uint64_t ib_alloc_bitmap; // TO DO replace with a real bitmap
 	struct drm_radeon_cs_priv cs;
+
+	struct radeon_pm_regs pmregs;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -527,6 +536,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 			     struct drm_file *file_priv,
 			     drm_radeon_kcmd_buffer_t *cmdbuf);
 
+extern int radeon_modeset_cp_suspend(struct drm_device *dev);
+extern int radeon_modeset_cp_resume(struct drm_device *dev);
+/* radeon_pm.c */
+int radeon_suspend(struct drm_device *dev, pm_message_t state);
+int radeon_resume(struct drm_device *dev);
 /* Flags for stats.boxes
  */
 #define RADEON_BOX_DMA_IDLE      0x1
@@ -1464,7 +1478,7 @@ do {									\
  * Ring control
  */
 
-#define RADEON_VERBOSE	0
+#define RADEON_VERBOSE	1
 
 #define RING_LOCALS	int write, _nr; unsigned int mask; u32 *ring;
 
@@ -1648,7 +1662,8 @@ extern int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 				  struct drm_file *file_priv);
 int radeon_gem_object_pin(struct drm_gem_object *obj,
-			  uint32_t alignment);
+			  uint32_t alignment, uint32_t pin_domain);
+int radeon_gem_object_unpin(struct drm_gem_object *obj);
 int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
 			      struct drm_file *file_priv);
 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
@@ -1670,6 +1685,8 @@ extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *
 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
 extern int radeon_cs_init(struct drm_device *dev);
 void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
+void radeon_init_memory_map(struct drm_device *dev);
+
 
 #define MARK_SAFE		1
 #define MARK_CHECK_OFFSET	2
-- 
cgit v1.2.3


From 8f23d4a44cdb17abff8f1ab3585e533ae0572224 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 18 Sep 2008 10:11:43 +1000
Subject: make text reserve 256k

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 662d9cc3..96f9a98c 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1478,7 +1478,7 @@ do {									\
  * Ring control
  */
 
-#define RADEON_VERBOSE	1
+#define RADEON_VERBOSE	0
 
 #define RING_LOCALS	int write, _nr; unsigned int mask; u32 *ring;
 
-- 
cgit v1.2.3


From 515aa0800cf2d91bdf4706463e0531c5081a2679 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 18 Sep 2008 10:17:27 +1000
Subject: radeon: do proper memory controller init and setup

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 96f9a98c..82d9d001 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -491,6 +491,7 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
 
 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
 
+extern int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv);
 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
 
 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
-- 
cgit v1.2.3


From 34af71c42a66e5ef6a9a08250ca541030ca3cc4f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 18 Sep 2008 16:07:41 -0400
Subject: radeon: add function to configure PCIE lanes

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 82d9d001..25a07e30 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1298,6 +1298,7 @@ int radeon_resume(struct drm_device *dev);
 
 extern u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
+extern u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr);
 
 #define RADEON_WRITE_P(reg, val, mask)		\
 do {						\
-- 
cgit v1.2.3


From 09b2dfcedc8cb35444567626131ccc25db79a8c6 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 26 Sep 2008 17:20:04 -0400
Subject: radeon: make atom on r4xx a module option

default is legacy modesetting.  pass module option r4xx_atom
to try using atom on r4xx.
---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 25a07e30..3490ddbe 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -456,6 +456,7 @@ typedef struct drm_radeon_kcmd_buffer {
 
 extern int radeon_no_wb;
 extern int radeon_dynclks;
+extern int radeon_r4xx_atom;
 extern struct drm_ioctl_desc radeon_ioctls[];
 extern int radeon_max_ioctl;
 
-- 
cgit v1.2.3


From d958cd7bb95558aa6c49824e2ae2b302f1433d2e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 16 Oct 2008 10:51:31 +1000
Subject: radeon: use discardable flags on no backing store objects

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 3490ddbe..c37f23d6 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1672,7 +1672,7 @@ int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
-					       int initial_domain);
+					       int initial_domain, bool discardable);
 int radeon_modeset_init(struct drm_device *dev);
 void radeon_modeset_cleanup(struct drm_device *dev);
 extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr);
-- 
cgit v1.2.3


From 26076bf24a4e720e389d0a3ea616a8350397fdfc Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 16 Oct 2008 10:59:31 +1000
Subject: radeon: add initial agp support.

This add agpmode command line option.
---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index c37f23d6..a6ce129d 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -459,6 +459,7 @@ extern int radeon_dynclks;
 extern int radeon_r4xx_atom;
 extern struct drm_ioctl_desc radeon_ioctls[];
 extern int radeon_max_ioctl;
+extern int radeon_agpmode;
 
 /* Check whether the given hardware address is inside the framebuffer or the
  * GART area.
-- 
cgit v1.2.3


From 48f222751643a349924ba3e6c26890310822f89c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:25:32 +1000
Subject: radeon: export radeon_modeset

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index a6ce129d..3be99eb3 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -460,6 +460,7 @@ extern int radeon_r4xx_atom;
 extern struct drm_ioctl_desc radeon_ioctls[];
 extern int radeon_max_ioctl;
 extern int radeon_agpmode;
+extern int radeon_modeset;
 
 /* Check whether the given hardware address is inside the framebuffer or the
  * GART area.
-- 
cgit v1.2.3


From 3fd0e1483ebe640b69da888e286ea85d11539b46 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:29:22 +1000
Subject: radeon: fixup scratch register interactions properly

---
 shared-core/radeon_drv.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 3be99eb3..2d592e45 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -733,11 +733,11 @@ int radeon_resume(struct drm_device *dev);
 
 #define RADEON_SCRATCHOFF( x )		(RADEON_SCRATCH_REG_OFFSET + 4*(x))
 
-#define GET_SCRATCH( x )	(dev_priv->writeback_works ?			\
-				 (dev_priv->mm.ring_read.bo ? \
-				  readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(x)) : \
-				  DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
-				 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
+#define GET_SCRATCH( x ) (dev_priv->writeback_works ?			\
+			 (dev_priv->mm.ring_read.bo ? \
+			  readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(x)) : \
+			  DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
+			 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
 
 #define RADEON_CRTC_CRNT_FRAME 0x0214
 #define RADEON_CRTC2_CRNT_FRAME 0x0314
@@ -1607,7 +1607,7 @@ extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
 
 /* Breadcrumb - swi irq */
-#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
+#define READ_BREADCRUMB(dev_priv) GET_SCRATCH(3)
 
 static inline int radeon_update_breadcrumb(struct drm_device *dev)
 {
-- 
cgit v1.2.3


From 1c817cc3fc09abe93539413130de3875e4c7eafe Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:32:39 +1000
Subject: radeon: pull bus master enable into its own function

---
 shared-core/radeon_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 2d592e45..0d5f762b 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1691,7 +1691,7 @@ extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *
 extern int radeon_cs_init(struct drm_device *dev);
 void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
 void radeon_init_memory_map(struct drm_device *dev);
-
+void radeon_enable_bm(struct drm_radeon_private *dev_priv);
 
 #define MARK_SAFE		1
 #define MARK_CHECK_OFFSET	2
-- 
cgit v1.2.3


From 624da91277ee33936ea3cfaf20e7f6775293deb2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:33:12 +1000
Subject: radeon: add r423 bits to modesetting

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 0d5f762b..17c0c297 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1644,6 +1644,7 @@ static inline int radeon_update_breadcrumb(struct drm_device *dev)
 				  (dev_priv->chip_family == CHIP_R350)  || \
 				  (dev_priv->chip_family == CHIP_RV380) || \
 				  (dev_priv->chip_family == CHIP_R420)  || \
+				  (dev_priv->chip_family == CHIP_R423)  || \
 				  (dev_priv->chip_family == CHIP_RV410) || \
 				  (dev_priv->chip_family == CHIP_RS400) || \
 				  (dev_priv->chip_family == CHIP_RS480))
-- 
cgit v1.2.3


From 8b2925468d326ab6fa31a312e845a3bc71343106 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:39:53 +1000
Subject: radeon: make new CS2 command submission interface port older
 interface to this

---
 shared-core/radeon_drv.h | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 17c0c297..b741953b 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -294,6 +294,23 @@ struct drm_radeon_master_private {
 #define RADEON_FLUSH_EMITED	(1 < 0)
 #define RADEON_PURGE_EMITED	(1 < 1)
 
+struct drm_radeon_kernel_chunk {
+	uint32_t chunk_id;
+	uint32_t length_dw;
+	uint32_t __user *chunk_data;
+	uint32_t *kdata;
+};
+
+struct drm_radeon_cs_parser {
+	struct drm_device *dev;
+	struct drm_file *file_priv;
+	uint32_t num_chunks;
+	struct drm_radeon_kernel_chunk *chunks;
+	int ib_index;
+	int reloc_index;
+	void *ib;
+};
+
 /* command submission struct */
 struct drm_radeon_cs_priv {
 	uint32_t id_wcnt;
@@ -301,21 +318,22 @@ struct drm_radeon_cs_priv {
 	uint32_t id_last_wcnt;
 	uint32_t id_last_scnt;
 
-	int (*parse)(struct drm_device *dev, struct drm_file *file_priv,
-		     void *ib, uint32_t *packets, uint32_t dwords);
+	int (*parse)(struct drm_radeon_cs_parser *parser);
 	void (*id_emit)(struct drm_device *dev, uint32_t *id);
 	uint32_t (*id_last_get)(struct drm_device *dev);
 	/* this ib handling callback are for hidding memory manager drm
 	 * from memory manager less drm, free have to emit ib discard
 	 * sequence into the ring */
-	int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords, uint32_t *card_offset);
+	int (*ib_get)(struct drm_radeon_cs_parser *parser, uint32_t *card_offset);
 	uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
-	void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
+	void (*ib_free)(struct drm_radeon_cs_parser *parser);
 	/* do a relocation either MM or non-MM */
-	int (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
-			 uint32_t *reloc, uint32_t *offset);
+	int (*relocate)(struct drm_radeon_cs_parser *parser,
+			uint32_t *reloc, uint32_t *offset);
 };
 
+
+
 struct radeon_pm_regs {
 	uint32_t crtc_ext_cntl;
 	uint32_t bios_scratch[8];
@@ -1689,6 +1707,7 @@ extern int radeon_master_create(struct drm_device *dev, struct drm_master *maste
 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
+extern int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
 extern int radeon_cs_init(struct drm_device *dev);
 void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
 void radeon_init_memory_map(struct drm_device *dev);
-- 
cgit v1.2.3


From 4ccec67a239517458bace47bf08f6770393abb37 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:42:01 +1000
Subject: radeon: remove unused gem indirect ioctl

---
 shared-core/radeon_drv.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index b741953b..73e5a261 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1688,8 +1688,6 @@ extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_object_pin(struct drm_gem_object *obj,
 			  uint32_t alignment, uint32_t pin_domain);
 int radeon_gem_object_unpin(struct drm_gem_object *obj);
-int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
-			      struct drm_file *file_priv);
 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
-- 
cgit v1.2.3


From fc25c81eab2d847c854e0a44cae29f8c2213bba6 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:43:29 +1000
Subject: radeon: rs480 fixes for bus mastering

---
 shared-core/radeon_drv.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 73e5a261..85a22e9f 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -591,7 +591,11 @@ int radeon_resume(struct drm_device *dev);
 #	define RADEON_SCISSOR_2_ENABLE		(1 << 30)
 
 #define RADEON_BUS_CNTL			0x0030
+/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 #	define RADEON_BUS_MASTER_DIS		(1 << 6)
+/* rs600/rs690/rs740 */
+#	define RS600_BUS_MASTER_DIS		(1 << 14)
+#	define RS600_MSI_REARM		        (1 << 20)
 
 #define RADEON_CLOCK_CNTL_DATA		0x000c
 #	define RADEON_PLL_WR_EN			(1 << 7)
@@ -1053,6 +1057,7 @@ int radeon_resume(struct drm_device *dev);
 
 #define RADEON_AIC_CNTL			0x01d0
 #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
+#	define RS400_MSI_REARM	                (1 << 3)
 #define RADEON_AIC_STAT			0x01d4
 #define RADEON_AIC_PT_BASE		0x01d8
 #define RADEON_AIC_LO_ADDR		0x01dc
-- 
cgit v1.2.3


From 31f8d4218c0f6455751d8bbc788172912359b0df Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:44:03 +1000
Subject: radeon: add wait rendering API

---
 shared-core/radeon_drv.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 85a22e9f..aa178d4d 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1695,6 +1695,8 @@ int radeon_gem_object_pin(struct drm_gem_object *obj,
 int radeon_gem_object_unpin(struct drm_gem_object *obj);
 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
+int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv);
 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
 					       int initial_domain, bool discardable);
 int radeon_modeset_init(struct drm_device *dev);
-- 
cgit v1.2.3


From 4ef8ace9a96bd6bb4040ef5c4c3ea5572d7129e1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:45:43 +1000
Subject: radeon: add proc debugging for interrupts/ring

---
 shared-core/radeon_drv.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index aa178d4d..8f77c850 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -459,6 +459,7 @@ typedef struct drm_radeon_private {
 	struct drm_radeon_cs_priv cs;
 
 	struct radeon_pm_regs pmregs;
+	atomic_t irq_received;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -1718,6 +1719,8 @@ void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master
 void radeon_init_memory_map(struct drm_device *dev);
 void radeon_enable_bm(struct drm_radeon_private *dev_priv);
 
+extern int radeon_gem_proc_init(struct drm_minor *minor);
+extern void radeon_gem_proc_cleanup(struct drm_minor *minor);
 #define MARK_SAFE		1
 #define MARK_CHECK_OFFSET	2
 #define MARK_CHECK_SCISSOR	3
-- 
cgit v1.2.3


From 31b8a640db9b55638bf9967f0d78ec665fa8839f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:46:54 +1000
Subject: radeon: overhaul ring interactions

emit in 16-dword blocks, emit irqs at same time as everything else
---
 shared-core/radeon_drv.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 8f77c850..83478a27 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -308,6 +308,7 @@ struct drm_radeon_cs_parser {
 	struct drm_radeon_kernel_chunk *chunks;
 	int ib_index;
 	int reloc_index;
+	uint32_t card_offset;
 	void *ib;
 };
 
@@ -319,12 +320,12 @@ struct drm_radeon_cs_priv {
 	uint32_t id_last_scnt;
 
 	int (*parse)(struct drm_radeon_cs_parser *parser);
-	void (*id_emit)(struct drm_device *dev, uint32_t *id);
+	void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id);
 	uint32_t (*id_last_get)(struct drm_device *dev);
 	/* this ib handling callback are for hidding memory manager drm
 	 * from memory manager less drm, free have to emit ib discard
 	 * sequence into the ring */
-	int (*ib_get)(struct drm_radeon_cs_parser *parser, uint32_t *card_offset);
+	int (*ib_get)(struct drm_radeon_cs_parser *parser);
 	uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
 	void (*ib_free)(struct drm_radeon_cs_parser *parser);
 	/* do a relocation either MM or non-MM */
@@ -459,6 +460,7 @@ typedef struct drm_radeon_private {
 	struct drm_radeon_cs_priv cs;
 
 	struct radeon_pm_regs pmregs;
+	int irq_emitted;
 	atomic_t irq_received;
 } drm_radeon_private_t;
 
-- 
cgit v1.2.3


From 0e1df6216e7ce3a69d4311e4685613e57129285f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:52:25 +1000
Subject: radeon: add mtrr support for VRAM aperture.

---
 shared-core/radeon_drv.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 83478a27..c6ebf9b6 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -462,6 +462,9 @@ typedef struct drm_radeon_private {
 	struct radeon_pm_regs pmregs;
 	int irq_emitted;
 	atomic_t irq_received;
+
+	uint32_t aper_size;
+	int vram_mtrr;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
-- 
cgit v1.2.3


From 68fcb7770efc20b9e27b1724e2fb5ac112a5330e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 3 Nov 2008 09:58:12 +1000
Subject: radeon: make build again

---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index c6ebf9b6..a95ab152 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -124,6 +124,7 @@ enum radeon_family {
 	CHIP_RV350,
 	CHIP_RV380,
 	CHIP_R420,
+	CHIP_R423,
 	CHIP_RV410,
 	CHIP_RS400,
 	CHIP_RS480,
-- 
cgit v1.2.3


From 08ef5b5e677579892a454d44a96a12dc771b56ac Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 10 Nov 2008 15:24:42 +1000
Subject: radeon: force all ring writes to 16-dword alignment.

---
 shared-core/radeon_drv.h | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index a95ab152..828ad3f9 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -219,7 +219,6 @@ typedef struct drm_radeon_ring_buffer {
 	int rptr_update; /* Double Words */
 	int rptr_update_l2qw; /* log2 Quad Words */
 
-	int fetch_size; /* Double Words */
 	int fetch_size_l2ow; /* log2 Oct Words */
 
 	u32 tail;
@@ -1515,15 +1514,16 @@ do {									\
 
 #define RADEON_VERBOSE	0
 
-#define RING_LOCALS	int write, _nr; unsigned int mask; u32 *ring;
+#define RING_LOCALS	int write, _nr, _align_nr; unsigned int mask; u32 *ring;
 
 #define BEGIN_RING( n ) do {						\
 	if ( RADEON_VERBOSE ) {						\
 		DRM_INFO( "BEGIN_RING( %d )\n", (n));			\
 	}								\
-	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
+	_align_nr = (n + 0xf) & ~0xf;					\
+	if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) {	\
 		COMMIT_RING();						\
-		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
+		radeon_wait_ring(dev_priv, _align_nr * sizeof(u32));	\
 	}								\
 	_nr = n; dev_priv->ring.space -= (n) * sizeof(u32);		\
 	ring = dev_priv->ring.start;					\
@@ -1540,19 +1540,14 @@ do {									\
 		DRM_ERROR(						\
 			"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",	\
 			((dev_priv->ring.tail + _nr) & mask),		\
-			write, __LINE__);						\
+			write, __LINE__);				\
 	} else								\
 		dev_priv->ring.tail = write;				\
 } while (0)
 
 #define COMMIT_RING() do {						\
-	/* Flush writes to ring */					\
-	DRM_MEMORYBARRIER();						\
-	GET_RING_HEAD( dev_priv );					\
-	RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );		\
-	/* read from PCI bus to ensure correct posting */		\
-	RADEON_READ( RADEON_CP_RB_RPTR );				\
-} while (0)
+		radeon_commit_ring(dev_priv);				\
+	} while(0)
 
 #define OUT_RING( x ) do {						\
 	if ( RADEON_VERBOSE ) {						\
@@ -1731,6 +1726,8 @@ extern void radeon_gem_proc_cleanup(struct drm_minor *minor);
 #define MARK_CHECK_OFFSET	2
 #define MARK_CHECK_SCISSOR	3
 
+extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
+
 extern int r300_check_range(unsigned reg, int count);
 extern int r300_get_reg_flags(unsigned reg);
 #endif				/* __RADEON_DRV_H__ */
-- 
cgit v1.2.3


From 758376e6eb2155605ad502d0dc5147c74f3c47a6 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 10 Nov 2008 15:25:12 +1000
Subject: radeon: disable HDP read cache for now

---
 shared-core/radeon_drv.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 828ad3f9..cd683795 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -791,8 +791,10 @@ int radeon_resume(struct drm_device *dev);
 #       define R500_DISPLAY_INT_STATUS          (1 << 0)
 
 #define RADEON_HOST_PATH_CNTL               0x0130
-#       define RADEON_HDP_SOFT_RESET        (1 << 26)
 #       define RADEON_HDP_APER_CNTL         (1 << 23)
+#       define RADEON_HP_LIN_RD_CACHE_DIS   (1 << 24)
+#       define RADEON_HDP_SOFT_RESET        (1 << 26)
+#       define RADEON_HDP_READ_BUFFER_INVALIDATED (1 << 27)
 
 #define RADEON_NB_TOM                       0x15c
 
-- 
cgit v1.2.3


From 15464f5181538d01e8fc016211daa1a824b89531 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 10 Nov 2008 15:38:32 +1000
Subject: radeon: add gart useable size to report to userspace

---
 shared-core/radeon_drv.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index cd683795..cf3084e1 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -274,6 +274,8 @@ struct radeon_mm_info {
 	uint64_t gart_start;
 	uint64_t gart_size;
 
+	uint64_t gart_useable;
+
 	void *pcie_table_backup;
 	
 	struct radeon_mm_obj pcie_table;
-- 
cgit v1.2.3


From 7270731a8b7ebe11fe6df4f368c2ed613a530b52 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <glisse@freedesktop.org>
Date: Sun, 16 Nov 2008 18:11:00 +0100
Subject: radeon: protect cs ioctl atomic part with a mutex

A small subset of CS need to be atomic (relocation+IB commit to
ring) right now, because of the way relocation are handled, we
need to protect the whole ioctl.
---
 shared-core/radeon_drv.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/radeon_drv.h')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index cf3084e1..fdf321d1 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -316,6 +316,7 @@ struct drm_radeon_cs_parser {
 
 /* command submission struct */
 struct drm_radeon_cs_priv {
+	struct mutex cs_mutex;
 	uint32_t id_wcnt;
 	uint32_t id_scnt;
 	uint32_t id_last_wcnt;
-- 
cgit v1.2.3