From 1a8406795052e3ec49e400465f3211d04fd9dd86 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 30 Apr 2008 16:03:15 -0700
Subject: Hacking towards hooking up execbuffer.

---
 shared-core/i915_drm.h | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index de463614..1a70010b 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -176,6 +176,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_MMIO		0x10
 #define DRM_I915_HWS_ADDR	0x11
 #define DRM_I915_EXECBUFFER	0x12
+#define DRM_I915_MM_INIT	0x13
+#define DRM_I915_MM_EXECBUFFER	0x14
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -195,6 +197,8 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 #define DRM_IOCTL_I915_EXECBUFFER	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
+#define DRM_IOCTL_I915_MM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_MM_INIT, struct drm_i915_mm_init)
+#define DRM_IOCTL_I915_MM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_MM_INIT, struct drm_i915_mm_execbuffer)
 
 /* Asynchronous page flipping:
  */
@@ -394,4 +398,85 @@ struct drm_i915_execbuffer {
 	struct drm_fence_arg fence_arg;
 };
 
+struct drm_i915_mm_init {
+	/**
+	 * Beginning offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	off_t gtt_start;
+	/**
+	 * Ending offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	off_t gtt_end;
+};
+
+struct drm_i915_relocation_entry {
+	/**
+	 * Handle of the buffer being pointed to by this relocation entry.
+	 *
+	 * It's appealing to make this be an index into the mm_validate_entry
+	 * list to refer to the buffer, but handle lookup should be O(1) anyway,
+	 * and prevents O(n) search in userland to find what that index is.
+	 */
+	uint32_t target_buffer;
+
+	/** Offset in the buffer the relocation entry will be written into */
+	uint32_t offset;
+
+	/**
+	 * Value to be added to the offset of the target buffer to make up
+	 * the relocation entry.
+	 */
+	uint32_t delta;
+
+	/**
+	 * Offset value of the target buffer that the relocation entry was last
+	 * written as.
+	 *
+	 * If the buffer has the same offset as last time, we can skip syncing
+	 * and writing the relocation.  This value is written back out by
+	 * the execbuffer ioctl when the relocation is written.
+	 */
+	uint32_t presumed_offset;
+};
+
+struct drm_i915_mm_validate_entry {
+	/**
+	 * User's handle for a buffer to be bound into the GTT for this
+	 * operation.
+	 */
+	uint32_t buffer_handle;
+	/**
+	 * Returned value of the updated offset of the buffer, for future
+	 * presumed_offset writes.
+	 */
+	uint32_t buffer_offset;
+	/** List of relocations to be performed on this buffer */
+	struct drm_i915_relocation_entry *relocs;
+	uint32_t relocation_count;
+};
+
+struct drm_i915_mm_execbuffer {
+	/**
+	 * List of buffers to be validated wit their relocations to be
+	 * performend on them.
+	 *
+	 * These buffers must be listed in an order such that all relocations
+	 * a buffer is performing refer to buffers that have already appeared
+	 * in the validate list.
+	 */
+	struct drm_i915_mm_validate_entry *buffers;
+	uint32_t buffer_count;
+
+	/** Offset in the batchbuffer to start execution from. */
+	uint32_t batch_start_offset;
+	/** Bytes used in batchbuffer from batch_start_offset */
+	uint32_t batch_len;
+	uint32_t DR1;
+	uint32_t DR4;
+	uint32_t num_cliprects;
+	struct drm_clip_rect *cliprects;
+};
+
 #endif				/* _I915_DRM_H_ */
-- 
cgit v1.2.3


From 2140e102f942edf7982cee2a3f00caf234551687 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 1 May 2008 11:39:06 -0700
Subject: checkpoint: rename to GEM and a few more i915 bits.

---
 shared-core/i915_drm.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 1a70010b..4c241fc5 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -176,8 +176,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_MMIO		0x10
 #define DRM_I915_HWS_ADDR	0x11
 #define DRM_I915_EXECBUFFER	0x12
-#define DRM_I915_MM_INIT	0x13
-#define DRM_I915_MM_EXECBUFFER	0x14
+#define DRM_I915_GEM_INIT	0x13
+#define DRM_I915_GEM_EXECBUFFER	0x14
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -197,8 +197,8 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 #define DRM_IOCTL_I915_EXECBUFFER	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
-#define DRM_IOCTL_I915_MM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_MM_INIT, struct drm_i915_mm_init)
-#define DRM_IOCTL_I915_MM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_MM_INIT, struct drm_i915_mm_execbuffer)
+#define DRM_IOCTL_I915_MM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_MM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_execbuffer)
 
 /* Asynchronous page flipping:
  */
@@ -398,7 +398,7 @@ struct drm_i915_execbuffer {
 	struct drm_fence_arg fence_arg;
 };
 
-struct drm_i915_mm_init {
+struct drm_i915_gem_init {
 	/**
 	 * Beginning offset in the GTT to be managed by the DRM memory
 	 * manager.
@@ -411,7 +411,7 @@ struct drm_i915_mm_init {
 	off_t gtt_end;
 };
 
-struct drm_i915_relocation_entry {
+struct drm_i915_gem_relocation_entry {
 	/**
 	 * Handle of the buffer being pointed to by this relocation entry.
 	 *
@@ -441,7 +441,7 @@ struct drm_i915_relocation_entry {
 	uint32_t presumed_offset;
 };
 
-struct drm_i915_mm_validate_entry {
+struct drm_i915_gem_validate_entry {
 	/**
 	 * User's handle for a buffer to be bound into the GTT for this
 	 * operation.
@@ -453,11 +453,11 @@ struct drm_i915_mm_validate_entry {
 	 */
 	uint32_t buffer_offset;
 	/** List of relocations to be performed on this buffer */
-	struct drm_i915_relocation_entry *relocs;
+	struct drm_i915_gem_relocation_entry *relocs;
 	uint32_t relocation_count;
 };
 
-struct drm_i915_mm_execbuffer {
+struct drm_i915_gem_execbuffer {
 	/**
 	 * List of buffers to be validated wit their relocations to be
 	 * performend on them.
@@ -466,7 +466,7 @@ struct drm_i915_mm_execbuffer {
 	 * a buffer is performing refer to buffers that have already appeared
 	 * in the validate list.
 	 */
-	struct drm_i915_mm_validate_entry *buffers;
+	struct drm_i915_gem_validate_entry *buffers;
 	uint32_t buffer_count;
 
 	/** Offset in the batchbuffer to start execution from. */
-- 
cgit v1.2.3


From ccd1bae0f676490a88240c62f02e072d2cf3b030 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 1 May 2008 15:22:21 -0700
Subject: checkpoint: relocations support.

---
 shared-core/i915_drm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 4c241fc5..52d1f31f 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -419,7 +419,7 @@ struct drm_i915_gem_relocation_entry {
 	 * list to refer to the buffer, but handle lookup should be O(1) anyway,
 	 * and prevents O(n) search in userland to find what that index is.
 	 */
-	uint32_t target_buffer;
+	uint32_t target_handle;
 
 	/** Offset in the buffer the relocation entry will be written into */
 	uint32_t offset;
-- 
cgit v1.2.3


From 793549116ee6e9202fc7e474bd382eb19ffeb87f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 1 May 2008 15:40:02 -0700
Subject: Add pin/unpin object ioctls for gem.

---
 shared-core/i915_drm.h | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 52d1f31f..4d113e4c 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -178,6 +178,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_EXECBUFFER	0x12
 #define DRM_I915_GEM_INIT	0x13
 #define DRM_I915_GEM_EXECBUFFER	0x14
+#define DRM_I915_GEM_PIN	0x15
+#define DRM_I915_GEM_UNPIN	0x16
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -197,8 +199,10 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 #define DRM_IOCTL_I915_EXECBUFFER	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
-#define DRM_IOCTL_I915_MM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
-#define DRM_IOCTL_I915_MM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
+#define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 
 /* Asynchronous page flipping:
  */
@@ -479,4 +483,18 @@ struct drm_i915_gem_execbuffer {
 	struct drm_clip_rect *cliprects;
 };
 
+struct drm_i915_gem_pin {
+	/** Handle of the buffer to be pinned. */
+	uint32_t handle;
+
+	/** Returned GTT offset of the buffer. */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_unpin {
+	/** Handle of the buffer to be unpinned. */
+	uint32_t handle;
+};
+
+
 #endif				/* _I915_DRM_H_ */
-- 
cgit v1.2.3


From 30efad5113944681c1abd6452e10355c105e9c39 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Thu, 1 May 2008 20:31:16 -0700
Subject: Fix gem ioctls to be 32/64-bit clean.

mixed 32/64 bit systems need 'special' help for ioctl where the user-space
and kernel-space datatypes differ. Fixing the datatypes to be the same size,
and align the same way for both 32 and 64-bit ppc and x86 environments will
elimiante the need to have magic 32/64-bit ioctl translation code.
---
 shared-core/i915_drm.h | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 4d113e4c..91461c41 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -407,12 +407,12 @@ struct drm_i915_gem_init {
 	 * Beginning offset in the GTT to be managed by the DRM memory
 	 * manager.
 	 */
-	off_t gtt_start;
+	uint64_t gtt_start;
 	/**
 	 * Ending offset in the GTT to be managed by the DRM memory
 	 * manager.
 	 */
-	off_t gtt_end;
+	uint64_t gtt_end;
 };
 
 struct drm_i915_gem_relocation_entry {
@@ -425,15 +425,15 @@ struct drm_i915_gem_relocation_entry {
 	 */
 	uint32_t target_handle;
 
-	/** Offset in the buffer the relocation entry will be written into */
-	uint32_t offset;
-
 	/**
 	 * Value to be added to the offset of the target buffer to make up
 	 * the relocation entry.
 	 */
 	uint32_t delta;
 
+	/** Offset in the buffer the relocation entry will be written into */
+	uint64_t offset;
+
 	/**
 	 * Offset value of the target buffer that the relocation entry was last
 	 * written as.
@@ -442,7 +442,7 @@ struct drm_i915_gem_relocation_entry {
 	 * and writing the relocation.  This value is written back out by
 	 * the execbuffer ioctl when the relocation is written.
 	 */
-	uint32_t presumed_offset;
+	uint64_t presumed_offset;
 };
 
 struct drm_i915_gem_validate_entry {
@@ -457,8 +457,9 @@ struct drm_i915_gem_validate_entry {
 	 */
 	uint32_t buffer_offset;
 	/** List of relocations to be performed on this buffer */
-	struct drm_i915_gem_relocation_entry *relocs;
+	uint64_t relocs_ptr;	/* struct drm_i915_gem_relocation_entry *relocs */
 	uint32_t relocation_count;
+	uint32_t pad;
 };
 
 struct drm_i915_gem_execbuffer {
@@ -470,7 +471,7 @@ struct drm_i915_gem_execbuffer {
 	 * a buffer is performing refer to buffers that have already appeared
 	 * in the validate list.
 	 */
-	struct drm_i915_gem_validate_entry *buffers;
+	uint64_t buffers_ptr;	/* struct drm_i915_gem_validate_entry *buffers */
 	uint32_t buffer_count;
 
 	/** Offset in the batchbuffer to start execution from. */
@@ -480,12 +481,13 @@ struct drm_i915_gem_execbuffer {
 	uint32_t DR1;
 	uint32_t DR4;
 	uint32_t num_cliprects;
-	struct drm_clip_rect *cliprects;
+	uint64_t cliprects_ptr;	/* struct drm_clip_rect *cliprects */
 };
 
 struct drm_i915_gem_pin {
 	/** Handle of the buffer to be pinned. */
 	uint32_t handle;
+	uint32_t pad;
 
 	/** Returned GTT offset of the buffer. */
 	uint64_t offset;
@@ -494,6 +496,7 @@ struct drm_i915_gem_pin {
 struct drm_i915_gem_unpin {
 	/** Handle of the buffer to be unpinned. */
 	uint32_t handle;
+	uint32_t pad;
 };
 
 
-- 
cgit v1.2.3


From 0d547c9ed92c0183f2c727496154baa2849f326e Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Thu, 1 May 2008 20:41:55 -0700
Subject: Add alignment to all aperture allocation requests.

When pinning buffers, or using execbuffer, allow the application to specify
the necessary aperture allocation alignment constraints.
---
 shared-core/i915_drm.h | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 91461c41..0c64e866 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -451,15 +451,18 @@ struct drm_i915_gem_validate_entry {
 	 * operation.
 	 */
 	uint32_t buffer_handle;
+	
+	/** List of relocations to be performed on this buffer */
+	uint32_t relocation_count;
+	uint64_t relocs_ptr;	/* struct drm_i915_gem_relocation_entry *relocs */
+	
+	/** Required alignment in graphics aperture */
+	uint64_t alignment;
 	/**
 	 * Returned value of the updated offset of the buffer, for future
 	 * presumed_offset writes.
 	 */
-	uint32_t buffer_offset;
-	/** List of relocations to be performed on this buffer */
-	uint64_t relocs_ptr;	/* struct drm_i915_gem_relocation_entry *relocs */
-	uint32_t relocation_count;
-	uint32_t pad;
+	uint64_t buffer_offset;
 };
 
 struct drm_i915_gem_execbuffer {
@@ -488,6 +491,9 @@ struct drm_i915_gem_pin {
 	/** Handle of the buffer to be pinned. */
 	uint32_t handle;
 	uint32_t pad;
+	
+	/** alignment required within the aperture */
+	uint64_t alignment;
 
 	/** Returned GTT offset of the buffer. */
 	uint64_t offset;
-- 
cgit v1.2.3


From 631e86c5c4ad9b2cdd40749ea3b351204a362c80 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Tue, 6 May 2008 14:43:49 -0700
Subject: Start coding up memory domains

---
 shared-core/i915_drm.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 0c64e866..302fc646 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -445,6 +445,28 @@ struct drm_i915_gem_relocation_entry {
 	uint64_t presumed_offset;
 };
 
+/**
+ * Intel memory domains
+ *
+ * Most of these just align with the various caches in
+ * the system and are used to flush and invalidate as
+ * objects end up cached in different domains.
+ *
+ * STOLEN is a domain for the stolen memory portion of the
+ * address space; those pages are accessible only through the
+ * GTT and, hence, look a lot like VRAM on a discrete card.
+ * We'll allow programs to move objects into stolen memory
+ * mostly as a way to demonstrate the VRAM capabilities of this
+ * API
+ */
+
+/* 0x00000001 is DRM_GEM_DOMAIN_CPU */
+#define DRM_GEM_DOMAIN_I915_RENDER	0x00000002	/* Render cache, used by 2D and 3D drawing */
+#define DRM_GEM_DOMAIN_I915_SAMPLER	0x00000004	/* Sampler cache, used by texture engine */
+#define DRM_GEM_DOMAIN_I915_COMMAND	0x00000008	/* Command queue, used to load batch buffers */
+#define DRM_GEM_DOMAIN_I915_INSTRUCTION	0x00000010	/* Instruction cache, used by shader programs */
+#define DRM_GEM_DOMAIN_I915_STOLEN	0x00000020	/* Stolen memory, needed by some objects */
+
 struct drm_i915_gem_validate_entry {
 	/**
 	 * User's handle for a buffer to be bound into the GTT for this
@@ -458,6 +480,11 @@ struct drm_i915_gem_validate_entry {
 	
 	/** Required alignment in graphics aperture */
 	uint64_t alignment;
+
+	/** Memory domains used in this execbuffer run */
+	uint32_t read_domains;
+	uint32_t write_domain;
+
 	/**
 	 * Returned value of the updated offset of the buffer, for future
 	 * presumed_offset writes.
-- 
cgit v1.2.3


From 5f5f01ed91f5ad50f2b38e11740a30441ac845a4 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 7 May 2008 12:46:06 -0700
Subject: GEM: Extend cache domain stuff for 965.

One of our MI_FLUSH bits is reserved on 965, being always implied, and there's
a vertex cache that was forgotten.
---
 shared-core/i915_drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 302fc646..8c3cd646 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -466,6 +466,7 @@ struct drm_i915_gem_relocation_entry {
 #define DRM_GEM_DOMAIN_I915_COMMAND	0x00000008	/* Command queue, used to load batch buffers */
 #define DRM_GEM_DOMAIN_I915_INSTRUCTION	0x00000010	/* Instruction cache, used by shader programs */
 #define DRM_GEM_DOMAIN_I915_STOLEN	0x00000020	/* Stolen memory, needed by some objects */
+#define DRM_GEM_DOMAIN_I915_VERTEX	0x00000040	/* Vertex address cache */
 
 struct drm_i915_gem_validate_entry {
 	/**
-- 
cgit v1.2.3


From 9af4c497433398fa4576a7c1c31036448cf4f24c Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Thu, 8 May 2008 10:44:02 -0700
Subject: [intel-gem] Move domains to relocation records. add set_domain ioctl.

Domain information is about buffer relationships, not buffer contents. That
means a relocation contains the domain information as it knows how the
source buffer references the target buffer.

This also adds the set_domain ioctl so that user space can move buffers to
the cpu domain.
---
 shared-core/i915_drm.h | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 8c3cd646..d71447e6 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -443,6 +443,20 @@ struct drm_i915_gem_relocation_entry {
 	 * the execbuffer ioctl when the relocation is written.
 	 */
 	uint64_t presumed_offset;
+
+	/**
+	 * Target memory domains read by this operation.
+	 */
+	uint32_t read_domains;
+
+	/**
+	 * Target memory domains written by this operation.
+	 *
+	 * Note that only one domain may be written by the whole
+	 * execbuffer operation, so that where there are conflicts,
+	 * the application will get -EINVAL back.
+	 */
+	uint32_t write_domain;
 };
 
 /**
@@ -451,13 +465,6 @@ struct drm_i915_gem_relocation_entry {
  * Most of these just align with the various caches in
  * the system and are used to flush and invalidate as
  * objects end up cached in different domains.
- *
- * STOLEN is a domain for the stolen memory portion of the
- * address space; those pages are accessible only through the
- * GTT and, hence, look a lot like VRAM on a discrete card.
- * We'll allow programs to move objects into stolen memory
- * mostly as a way to demonstrate the VRAM capabilities of this
- * API
  */
 
 /* 0x00000001 is DRM_GEM_DOMAIN_CPU */
@@ -465,8 +472,7 @@ struct drm_i915_gem_relocation_entry {
 #define DRM_GEM_DOMAIN_I915_SAMPLER	0x00000004	/* Sampler cache, used by texture engine */
 #define DRM_GEM_DOMAIN_I915_COMMAND	0x00000008	/* Command queue, used to load batch buffers */
 #define DRM_GEM_DOMAIN_I915_INSTRUCTION	0x00000010	/* Instruction cache, used by shader programs */
-#define DRM_GEM_DOMAIN_I915_STOLEN	0x00000020	/* Stolen memory, needed by some objects */
-#define DRM_GEM_DOMAIN_I915_VERTEX	0x00000040	/* Vertex address cache */
+#define DRM_GEM_DOMAIN_I915_VERTEX	0x00000020	/* Vertex address cache */
 
 struct drm_i915_gem_validate_entry {
 	/**
@@ -482,10 +488,6 @@ struct drm_i915_gem_validate_entry {
 	/** Required alignment in graphics aperture */
 	uint64_t alignment;
 
-	/** Memory domains used in this execbuffer run */
-	uint32_t read_domains;
-	uint32_t write_domain;
-
 	/**
 	 * Returned value of the updated offset of the buffer, for future
 	 * presumed_offset writes.
-- 
cgit v1.2.3


From a37ac493da1730436028ecc79a38513380ce15d0 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Sat, 10 May 2008 21:04:18 -0700
Subject: [intel-GEM] Clean up GEM ioctl naming.

Rename 'validate_entry' to 'exec_object', then clean up some field names in
structures (renaming buffer_offset to just offset, for example).
---
 shared-core/i915_drm.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index d71447e6..5f7cefeb 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -474,12 +474,12 @@ struct drm_i915_gem_relocation_entry {
 #define DRM_GEM_DOMAIN_I915_INSTRUCTION	0x00000010	/* Instruction cache, used by shader programs */
 #define DRM_GEM_DOMAIN_I915_VERTEX	0x00000020	/* Vertex address cache */
 
-struct drm_i915_gem_validate_entry {
+struct drm_i915_gem_exec_object {
 	/**
 	 * User's handle for a buffer to be bound into the GTT for this
 	 * operation.
 	 */
-	uint32_t buffer_handle;
+	uint32_t handle;
 	
 	/** List of relocations to be performed on this buffer */
 	uint32_t relocation_count;
@@ -489,10 +489,10 @@ struct drm_i915_gem_validate_entry {
 	uint64_t alignment;
 
 	/**
-	 * Returned value of the updated offset of the buffer, for future
+	 * Returned value of the updated offset of the object, for future
 	 * presumed_offset writes.
 	 */
-	uint64_t buffer_offset;
+	uint64_t offset;
 };
 
 struct drm_i915_gem_execbuffer {
-- 
cgit v1.2.3


From f650d7240a5b6eea8e605734f1211c20727c21d7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 12 May 2008 12:55:36 -0700
Subject: [GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.

---
 shared-core/i915_drm.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 5f7cefeb..b50471f3 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -420,8 +420,9 @@ struct drm_i915_gem_relocation_entry {
 	 * Handle of the buffer being pointed to by this relocation entry.
 	 *
 	 * It's appealing to make this be an index into the mm_validate_entry
-	 * list to refer to the buffer, but handle lookup should be O(1) anyway,
-	 * and prevents O(n) search in userland to find what that index is.
+	 * list to refer to the buffer, but this allows the driver to create
+	 * a relocation list for state buffers and not re-write it per
+	 * exec using the buffer.
 	 */
 	uint32_t target_handle;
 
@@ -497,7 +498,7 @@ struct drm_i915_gem_exec_object {
 
 struct drm_i915_gem_execbuffer {
 	/**
-	 * List of buffers to be validated wit their relocations to be
+	 * List of buffers to be validated with their relocations to be
 	 * performend on them.
 	 *
 	 * These buffers must be listed in an order such that all relocations
-- 
cgit v1.2.3


From 7cf3fd29fe058a0bfc2ba7e889d1b360398be161 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Sun, 25 May 2008 20:45:20 -0700
Subject: [intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.

This new ioctl returns whether re-using the buffer would force a wait.
---
 shared-core/i915_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index b50471f3..a8e09e72 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -180,6 +180,7 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_EXECBUFFER	0x14
 #define DRM_I915_GEM_PIN	0x15
 #define DRM_I915_GEM_UNPIN	0x16
+#define DRM_I915_GEM_BUSY	0x17
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -203,6 +204,7 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 #define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
+#define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 
 /* Asynchronous page flipping:
  */
@@ -536,5 +538,12 @@ struct drm_i915_gem_unpin {
 	uint32_t pad;
 };
 
+struct drm_i915_gem_busy {
+	/** Handle of the buffer to check for busy */
+	uint32_t handle;
+	
+	/** Return busy status (1 if busy, 0 if idle) */
+	uint32_t busy;
+};
 
 #endif				/* _I915_DRM_H_ */
-- 
cgit v1.2.3


From 56a96841d01d112d7d4adfebb572016398551ba8 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Fri, 6 Jun 2008 12:57:01 -0700
Subject: [intel-gem] Add explicit throttle ioctl

Instead of throttling and execbuffer time, have the application ask to
throttle explicitly. This allows the throttle to happen less often, and
without holding the DRM lock.
---
 shared-core/i915_drm.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 4712ea4f..0fa292d0 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -181,6 +181,7 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_PIN	0x15
 #define DRM_I915_GEM_UNPIN	0x16
 #define DRM_I915_GEM_BUSY	0x17
+#define DRM_I915_GEM_THROTTLE	0x18
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -205,6 +206,7 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 
 /* Asynchronous page flipping:
  */
-- 
cgit v1.2.3


From 2150da5d1a57d25d0f4bc39bb6c883d410f586d1 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 10 Jun 2008 15:30:23 -0700
Subject: [gem] Manage the ringbuffer from the kernel in the GEM case.

This requires that the X Server use the execbuf interface for buffer
submission, as it no longer has direct access to the ring.  This is
therefore a flag day for the gem interface.

This also adds enter/leavevt ioctls for use by the X Server.  These would
get stubbed out in a modesetting implementation, but are required while
in an environment where the device's state is only managed by the DRM while
X has the VT.
---
 shared-core/i915_drm.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 0fa292d0..ce01640a 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -182,6 +182,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_UNPIN	0x16
 #define DRM_I915_GEM_BUSY	0x17
 #define DRM_I915_GEM_THROTTLE	0x18
+#define DRM_I915_GEM_ENTERVT	0x19
+#define DRM_I915_GEM_LEAVEVT	0x20
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -207,6 +209,8 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 #define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
+#define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 
 /* Asynchronous page flipping:
  */
-- 
cgit v1.2.3


From 2655005762b8915d5f44d1d1ee7e6c2eb34841d7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 11 Jun 2008 14:42:40 -0700
Subject: [gem] Move potentially device-specific ioctls to the intel driver.

This is the create (may want location flags), pread/pwrite/mmap
(performance tuning hints), and set_domain (will 32 bits be enough for
everyone?) ioctls.  Left in the generic set are just flink/open/close.

The 2D driver must be updated for this change, and API but not ABI is broken
for 3D.  The driver version is bumped to mark this.
---
 shared-core/i915_drm.h | 101 ++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 92 insertions(+), 9 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index ce01640a..fe47708d 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -183,7 +183,12 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_BUSY	0x17
 #define DRM_I915_GEM_THROTTLE	0x18
 #define DRM_I915_GEM_ENTERVT	0x19
-#define DRM_I915_GEM_LEAVEVT	0x20
+#define DRM_I915_GEM_LEAVEVT	0x1a
+#define DRM_I915_GEM_CREATE	0x1b
+#define DRM_I915_GEM_PREAD	0x1c
+#define DRM_I915_GEM_PWRITE	0x1d
+#define DRM_I915_GEM_MMAP	0x1e
+#define DRM_I915_GEM_SET_DOMAIN	0x1f
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -211,6 +216,11 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
+#define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 
 /* Asynchronous page flipping:
  */
@@ -424,6 +434,73 @@ struct drm_i915_gem_init {
 	uint64_t gtt_end;
 };
 
+struct drm_i915_gem_create {
+	/**
+	 * Requested size for the object.
+	 *
+	 * The (page-aligned) allocated size for the object will be returned.
+	 */
+	uint64_t size;
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_i915_gem_pread {
+	/** Handle for the object being read. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to read from */
+	uint64_t offset;
+	/** Length of data to read */
+	uint64_t size;
+	/** Pointer to write the data into. */
+	uint64_t data_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_pwrite {
+	/** Handle for the object being written to. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to write to */
+	uint64_t offset;
+	/** Length of data to write */
+	uint64_t size;
+	/** Pointer to read the data from. */
+	uint64_t data_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_mmap {
+	/** Handle for the object being mapped. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset in the object to map. */
+	uint64_t offset;
+	/**
+	 * Length of data to map.
+	 *
+	 * The value will be page-aligned.
+	 */
+	uint64_t size;
+	/** Returned pointer the data was mapped at */
+	uint64_t addr_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_set_domain {
+	/** Handle for the object */
+	uint32_t handle;
+
+	/** New read domains */
+	uint32_t read_domains;
+
+	/** New write domain */
+	uint32_t write_domain;
+};
+
 struct drm_i915_gem_relocation_entry {
 	/**
 	 * Handle of the buffer being pointed to by this relocation entry.
@@ -469,20 +546,26 @@ struct drm_i915_gem_relocation_entry {
 	uint32_t write_domain;
 };
 
-/**
+/** @{
  * Intel memory domains
  *
  * Most of these just align with the various caches in
  * the system and are used to flush and invalidate as
  * objects end up cached in different domains.
  */
-
-/* 0x00000001 is DRM_GEM_DOMAIN_CPU */
-#define DRM_GEM_DOMAIN_I915_RENDER	0x00000002	/* Render cache, used by 2D and 3D drawing */
-#define DRM_GEM_DOMAIN_I915_SAMPLER	0x00000004	/* Sampler cache, used by texture engine */
-#define DRM_GEM_DOMAIN_I915_COMMAND	0x00000008	/* Command queue, used to load batch buffers */
-#define DRM_GEM_DOMAIN_I915_INSTRUCTION	0x00000010	/* Instruction cache, used by shader programs */
-#define DRM_GEM_DOMAIN_I915_VERTEX	0x00000020	/* Vertex address cache */
+/** CPU cache */
+#define I915_GEM_DOMAIN_CPU		0x00000001
+/** Render cache, used by 2D and 3D drawing */
+#define I915_GEM_DOMAIN_RENDER		0x00000002
+/** Sampler cache, used by texture engine */
+#define I915_GEM_DOMAIN_SAMPLER		0x00000004
+/** Command queue, used to load batch buffers */
+#define I915_GEM_DOMAIN_COMMAND		0x00000008
+/** Instruction cache, used by shader programs */
+#define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
+/** Vertex address cache */
+#define I915_GEM_DOMAIN_VERTEX		0x00000020
+/** @} */
 
 struct drm_i915_gem_exec_object {
 	/**
-- 
cgit v1.2.3


From 846d792ac10c4b2738bb5ff59e56df168b9921ff Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 11 Jun 2008 15:51:17 -0700
Subject: [gem] Another round of cleanups from checkpatch.pl

---
 shared-core/i915_drm.h | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index fe47708d..f16dc99f 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -573,11 +573,15 @@ struct drm_i915_gem_exec_object {
 	 * operation.
 	 */
 	uint32_t handle;
-	
-	/** List of relocations to be performed on this buffer */
+
+	/** Number of relocations to be performed on this buffer */
 	uint32_t relocation_count;
-	uint64_t relocs_ptr;	/* struct drm_i915_gem_relocation_entry *relocs */
-	
+	/**
+	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
+	 * the relocations to be performed in this buffer.
+	 */
+	uint64_t relocs_ptr;
+
 	/** Required alignment in graphics aperture */
 	uint64_t alignment;
 
@@ -593,11 +597,13 @@ struct drm_i915_gem_execbuffer {
 	 * List of buffers to be validated with their relocations to be
 	 * performend on them.
 	 *
+	 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
+	 *
 	 * These buffers must be listed in an order such that all relocations
 	 * a buffer is performing refer to buffers that have already appeared
 	 * in the validate list.
 	 */
-	uint64_t buffers_ptr;	/* struct drm_i915_gem_validate_entry *buffers */
+	uint64_t buffers_ptr;
 	uint32_t buffer_count;
 
 	/** Offset in the batchbuffer to start execution from. */
@@ -614,7 +620,7 @@ struct drm_i915_gem_pin {
 	/** Handle of the buffer to be pinned. */
 	uint32_t handle;
 	uint32_t pad;
-	
+
 	/** alignment required within the aperture */
 	uint64_t alignment;
 
@@ -631,7 +637,7 @@ struct drm_i915_gem_unpin {
 struct drm_i915_gem_busy {
 	/** Handle of the buffer to check for busy */
 	uint32_t handle;
-	
+
 	/** Return busy status (1 if busy, 0 if idle) */
 	uint32_t busy;
 };
-- 
cgit v1.2.3


From 52e5d24fae4af6f2f4a5304a516c8c5ab347a11b Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Fri, 20 Jun 2008 00:19:42 -0700
Subject: [intel-gem] Add DRM_IOCTL_I915_GEM_SW_FINISH to flag CPU writes

When a software fallback has completed, usermode must notify the kernel so
that any scanout buffers can be synchronized. This ioctl should be called
whenever a fallback completes to flush CPU and chipset caches.
---
 shared-core/i915_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index f16dc99f..fde474d7 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -189,6 +189,7 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_PWRITE	0x1d
 #define DRM_I915_GEM_MMAP	0x1e
 #define DRM_I915_GEM_SET_DOMAIN	0x1f
+#define DRM_I915_GEM_SW_FINISH	0x20
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -221,6 +222,7 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 #define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 
 /* Asynchronous page flipping:
  */
@@ -501,6 +503,11 @@ struct drm_i915_gem_set_domain {
 	uint32_t write_domain;
 };
 
+struct drm_i915_gem_sw_finish {
+	/** Handle for the object */
+	uint32_t handle;
+};
+
 struct drm_i915_gem_relocation_entry {
 	/**
 	 * Handle of the buffer being pointed to by this relocation entry.
@@ -565,6 +572,8 @@ struct drm_i915_gem_relocation_entry {
 #define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
 /** Vertex address cache */
 #define I915_GEM_DOMAIN_VERTEX		0x00000020
+/** GTT domain - aperture and scanout */
+#define I915_GEM_DOMAIN_GTT		0x00000040
 /** @} */
 
 struct drm_i915_gem_exec_object {
-- 
cgit v1.2.3


From a0474be4e78d678eb615b37aad355effb955ee19 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 11 Jul 2008 14:47:33 -0700
Subject: intel-gem: Add two new ioctls for managing tiling on objects.

Various chips have exciting interactions between the CPU and the GPU's
different ways of accessing interleaved memory, so we need some kernel
assistance in determining how it works.

Only fully tested on GM965 so far.
---
 shared-core/i915_drm.h | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index fde474d7..9feffeb5 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -190,6 +190,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_MMAP	0x1e
 #define DRM_I915_GEM_SET_DOMAIN	0x1f
 #define DRM_I915_GEM_SW_FINISH	0x20
+#define DRM_I915_GEM_SET_TILING	0x21
+#define DRM_I915_GEM_GET_TILING	0x22
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -223,6 +225,8 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 #define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 #define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 
 /* Asynchronous page flipping:
  */
@@ -651,4 +655,64 @@ struct drm_i915_gem_busy {
 	uint32_t busy;
 };
 
+#define I915_TILING_NONE	0
+#define I915_TILING_X		1
+#define I915_TILING_Y		2
+
+#define I915_BIT_6_SWIZZLE_NONE		0
+#define I915_BIT_6_SWIZZLE_9		1
+#define I915_BIT_6_SWIZZLE_9_10		2
+#define I915_BIT_6_SWIZZLE_9_11		3
+#define I915_BIT_6_SWIZZLE_9_10_11	4
+/* Not seen by userland */
+#define I915_BIT_6_SWIZZLE_UNKNOWN	5
+
+struct drm_i915_gem_set_tiling {
+	/** Handle of the buffer to have its tiling state updated */
+	uint32_t handle;
+
+	/**
+	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 *
+	 * This value is to be set on request, and will be updated by the
+	 * kernel on successful return with the actual chosen tiling layout.
+	 *
+	 * The tiling mode may be demoted to I915_TILING_NONE when the system
+	 * has bit 6 swizzling that can't be managed correctly by GEM.
+	 *
+	 * Buffer contents become undefined when changing tiling_mode.
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Stride in bytes for the object when in I915_TILING_X or
+	 * I915_TILING_Y.
+	 */
+	uint32_t stride;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
+struct drm_i915_gem_get_tiling {
+	/** Handle of the buffer to get tiling state for. */
+	uint32_t handle;
+
+	/**
+	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
 #endif				/* _I915_DRM_H_ */
-- 
cgit v1.2.3


From ccbaad52f79162a77d98d0dde00681b1dbf14165 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 30 Jul 2008 14:10:36 -0700
Subject: intel-gem: Replace version bump signalling GEM with
 I915_PARAM_HAS_GEM.

---
 shared-core/i915_drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core/i915_drm.h')

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index 9feffeb5..2801687c 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -280,6 +280,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 #define I915_PARAM_LAST_DISPATCH         3
 #define I915_PARAM_CHIPSET_ID            4
+#define I915_PARAM_HAS_GEM               5
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
cgit v1.2.3