From 109e2a10f260f3a5f78762bbedcaeb9b2ebde1c0 Mon Sep 17 00:00:00 2001 From: Wang Zhenyu Date: Tue, 5 Jun 2007 11:15:29 -0700 Subject: Add support for the G33, Q33, and Q35 chipsets. These require that the status page be referenced by a pointer in GTT, rather than phsyical memory. So, we have the X Server allocate that memory and tell us the address, instead. --- shared-core/drm_pciids.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core/drm_pciids.txt') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 4b07e4f6..ba02aa89 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -289,6 +289,9 @@ 0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G" 0x8086 0x2A02 CHIP_I9XX|CHIP_I965 "Intel i965GM" 0x8086 0x2A12 CHIP_I9XX|CHIP_I965 "Intel i965GME/GLE" +0x8086 0x29C2 CHIP_I9XX|CHIP_I915 "Intel G33" +0x8086 0x29B2 CHIP_I9XX|CHIP_I915 "Intel Q35" +0x8086 0x29D2 CHIP_I9XX|CHIP_I915 "Intel Q33" [imagine] 0x105d 0x2309 IMAGINE_128 "Imagine 128" -- cgit v1.2.3