/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
*
* References:
*
* !!!! FIXME !!!!
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* !!!! FIXME !!!!
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
#ifndef _RADEON_REG_H_
#define _RADEON_REG_H_
#define ATI_DATATYPE_VQ 0
#define ATI_DATATYPE_CI4 1
#define ATI_DATATYPE_CI8 2
#define ATI_DATATYPE_ARGB1555 3
#define ATI_DATATYPE_RGB565 4
#define ATI_DATATYPE_RGB888 5
#define ATI_DATATYPE_ARGB8888 6
#define ATI_DATATYPE_RGB332 7
#define ATI_DATATYPE_Y8 8
#define ATI_DATATYPE_RGB8 9
#define ATI_DATATYPE_CI16 10
#define ATI_DATATYPE_VYUY_422 11
#define ATI_DATATYPE_YVYU_422 12
#define ATI_DATATYPE_AYUV_444 14
#define ATI_DATATYPE_ARGB4444 15
/* Registers for 2D/Video/Overlay */
#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
#define RADEON_AGP_BASE 0x0170
#define RADEON_AGP_CNTL 0x0174
# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_STATUS_PCI_CONFIG 0x06
# define RADEON_CAP_LIST 0x100000
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
# define RADEON_AGP_ENABLE (1<<8)
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
#define RADEON_AGP_STATUS 0x0f5c /* PCI */
# define RADEON_AGP_1X_MODE 0x01
# define RADEON_AGP_2X_MODE 0x02
# define RADEON_AGP_4X_MODE 0x04
# define RADEON_AGP_FW_MODE 0x10
# define RADEON_AGP_MODE_MASK 0x17
# define RADEON_AGPv3_MODE 0x08
# define RADEON_AGPv3_4X_MODE 0x01
# define RADEON_AGPv3_8X_MODE 0x02
#define RADEON_ATTRDR 0x03c1 /* VGA */
#define RADEON_ATTRDW 0x03c0 /* VGA */
#define RADEON_ATTRX 0x03c0 /* VGA */
#define RADEON_AUX_SC_CNTL 0x1660
# define RADEON_AUX1_SC_EN (1 << 0)
# define RADEON_AUX1_SC_MODE_OR (0 << 1)
# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
# define RADEON_AUX2_SC_EN (1 << 2)
# define RADEON_AUX2_SC_MODE_OR (0 << 3)
# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
# define RADEON_AUX3_SC_EN (1 << 4)
# define RADEON_AUX3_SC_MODE_OR (0 << 5)
# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
#define RADEON_AUX1_SC_BOTTOM 0x1670
#define RADEON_AUX1_SC_LEFT 0x1664
#define RADEON_AUX1_SC_RIGHT 0x1668
#define RADEON_AUX1_SC_TOP 0x166c
#define RADEON_AUX2_SC_BOTTOM 0x1680
#define RADEON_AUX2_SC_LEFT 0x1674
#define RADEON_AUX2_SC_RIGHT 0x1678
#define RADEON_AUX2_SC_TOP 0x167c
#define RADEON_AUX3_SC_BOTTOM 0x1690
#define RADEON_AUX3_SC_LEFT 0x1684
#define RADEON_AUX3_SC_RIGHT 0x1688
#define RADEON_AUX3_SC_TOP 0x168c
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
#define RADEON_BASE_CODE 0x0f0b
#define RADEON_BIOS_0_SCRATCH 0x0010
# define RADEON_FP_PANEL_SCALABLE (1 << 16)
# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
# define RADEON_DISPLAY_ROT_MASK (3 << 28)
# define RADEON_DISPLAY_ROT_00 (0 << 28)
# define RADEON_DISPLAY_ROT_90 (1 << 28)
# define RADEON_DISPLAY_ROT_180 (2 << 28)
# define RADEON_DISPLAY_ROT_270 (3 << 28)
#define RADEON_BIOS_1_SCRATCH 0x0014
#define RADEON_BIOS_2_SCRATCH 0x0018
#define RADEON_BIOS_3_SCRATCH 0x001c
#define RADEON_BIOS_4_SCRATCH 0x0020
# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
# define RADEON_LCD1_ATTACHED (1 << 2)
# define RADEON_DFP1_ATTACHED (1 << 3)
# define RADEON_TV1_ATTACHED_MASK (3 << 4)
# define RADEON_TV1_ATTACHED_COMP (1 << 4)
# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
# define RADEON_DFP2_ATTACHED (1 << 11)
#define RADEON_BIOS_5_SCRATCH 0x0024
# define RADEON_LCD1_ON (1 << 0)
# define RADEON_CRT1_ON (1 << 1)
# define RADEON_TV1_ON (1 << 2)
# define RADEON_DFP1_ON (1 << 3)
# define RADEON_CRT2_ON (1 << 5)
# define RADEON_CV1_ON (1 << 6)
# define RADEON_DFP2_ON (1 << 7)
# define RADEON_LCD1_CRTC_MASK (1 << 8)
# define RADEON_LCD1_CRTC_SHIFT 8
# define RADEON_CRT1_CRTC_MASK (1 << 9)
# define RADEON_CRT1_CRTC_SHIFT 9
# define RADEON_TV1_CRTC_MASK (1 << 10)
# define RADEON_TV1_CRTC_SHIFT 10
# define RADEON_DFP1_CRTC_MASK (1 << 11)
# define RADEON_DFP1_CRTC_SHIFT 11
# define RADEON_CRT2_CRTC_MASK (1 << 12)
# define RADEON_CRT2_CRTC_SHIFT 12
# define RADEON_CV1_CRTC_MASK (1 << 13)
# define RADEON_CV1_CRTC_SHIFT 13
# define RADEON_DFP2_CRTC_MASK (1 << 14)
# define RADEON_DFP2_CRTC_SHIFT 14
#define RADEON_BIOS_6_SCRATCH 0x0028
# define RADEON_ACC_MODE_CHANGE (1 << 2)
# define RADEON_EXT_DESKTOP_MODE (1 << 3)
# define RADEON_LCD_DPMS_ON (1 << 20)
# define RADEON_CRT_DPMS_ON (1 << 21)
# define RADEON_TV_DPMS_ON (1 << 22)
# define RADEON_DFP_DPMS_ON (1 << 23)
# define RADEON_DPMS_MASK (3 << 24)
# define RADEON_DPMS_ON (0 << 24)
# define RADEON_DPMS_STANDBY (1 << 24)
# define RADEON_DPMS_SUSPEND (2 << 24)
# define RADEON_DPMS_OFF (3 << 24)
# define RADEON_SCREEN_BLANKING (1 << 26)
# define RADEON_DRIVER_CRITICAL (1 << 27)
# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
#define RADEON_BIOS_7_SCRATCH 0x002c
# define RADEON_SYS_HOTKEY (1 << 10)
# define RADEON_DRV_LOADED (1 << 12)
#define RADEON_BIOS_ROM 0x0f30 /* PCI */
#define RADEON_BIST 0x0f0f /* PCI */
#define RADEON_BRUSH_DATA0 0x1480
#define RADEON_BRUSH_DATA1 0x1484
#define RADEON_BRUSH_DATA10 0x14a8
#define RADEON_BRUSH_DATA11 0x14ac
#define RADEON_BRUSH_DATA12 0x14b0
#define RADEON_BRUSH_DATA13 0x14b4
#define RADEON_BRUSH_DATA14 0x14b8
#define RADEON_BRUSH_DATA15 0x14bc
#define RADEON_BRUSH_DATA16 0x14c0
#define RADEON_BRUSH_DATA17 0x14c4
#define RADEON_BRUSH_DATA18 0x14c8
#define RADEON_BRUSH_DATA19 0x14cc
#define RADEON_BRUSH_DATA2 0x1488
#define RADEON_BRUSH_DATA20 0x14d0
#define RADEON_BRUSH_DATA21 0x14d4
#define RADEON_BRUSH_DATA22 0x14d8
#define RADEON_BRUSH_DATA23 0x14dc
#define RADEON_BRUSH_DATA24 0x14e0
#define RADEON_BRUSH_DATA25 0x14e4
#define RADEON_BRUSH_DATA26 0x14e8
#define RADEON_BRUSH_DATA27 0x14ec
#define RADEON_BRUSH_DATA28 0x14f0
#define RADEON_BRUSH_DATA29 0x14f4
#define RADEON_BRUSH_DATA3 0x148c
#define RADEON_BRUSH_DATA30 0x14f8
#define RADEON_BRUSH_DATA31 0x14fc
#define RADEON_BRUSH_DATA32 0x1500
#define RADEON_BRUSH_DATA33 0x1504
#define RADEON_BRUSH_DATA34 0x1508
#define RADEON_BRUSH_DATA35 0x150c
#define RADEON_BRUSH_DATA36 0x1510
#define RADEON_BRUSH_DATA37 0x1514
#define RADEON_BRUSH_DATA38 0x1518
#define RADEON_BRUSH_DATA39 0x151c
#define RADEON_BRUSH_DATA4 0x1490
#define RADEON_BRUSH_DATA40 0x1520
#define RADEON_BRUSH_DATA41 0x1524
#define RADEON_BRUSH_DATA42 0x1528
#define RADEON_BRUSH_DATA43 0x152c
#define RADEON_BRUSH_DATA44 0x1530
#define RADEON_BRUSH_DATA45 0x1534
#define RADEON_BRUSH_DATA46 0x1538
#define RADEON_BRUSH_DATA47 0x153c
#define RADEON_BRUSH_DATA48 0x1540
#define RADEON_BRUSH_DATA49 0x1544
#define RADEON_BRUSH_DATA5 0x1494
#define RADEON_BRUSH_DATA50 0x1548
#define RADEON_BRUSH_DATA51 0x154c
#define RADEON_BRUSH_DATA52 0x1550
#define RADEON_BRUSH_DATA53 0x1554
#define RADEON_BRUSH_DATA54 0x1558
#define RADEON_BRUSH_DATA55 0x155c
#define RADEON_BRUSH_DATA56 0x1560
#define RADEON_BRUSH_DATA57 0x1564
#define RADEON_BRUSH_DATA58 0x1568
#define RADEON_BRUSH_DATA59 0x156c
#define RADEON_BRUSH_DATA6 0x1498
#define RADEON_BRUSH_DATA60 0x1570
#define RADEON_BRUSH_DATA61 0x1574
#define RADEON_BRUSH_DATA62 0x1578
#define RADEON_BRUSH_DATA63 0x157c
#define RADEON_BRUSH_DATA7 0x149c
#define RADEON_BRUSH_DATA8 0x14a0
#define RADEON_BRUSH_DATA9 0x14a4
#define RADEON_BRUSH_SCALE 0x1470
#define RADEON_BRUSH_Y_X 0x1474
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
# define RADEON_BUS_RD_ABORT_EN (1 << 25)
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define RADEON_BUS_WRT_BURST (1 << 29)
# define RADEON_BUS_READ_BURST (1 << 30)
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
//#define RADEON_PCIE_INDEX 0x0030
//#define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
#define RADEON_CACHE_CNTL 0x1724
#define RADEON_CACHE_LINE 0x0f0c /* PCI */
#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
#define RADEON_CLOCK_CNTL_DATA 0x000c
#define RADEON_CLOCK_CNTL_INDEX 0x0008
# define RADEON_PLL_WR_EN (1 << 7)
# define RADEON_PLL_DIV_SEL (3 << 8)
# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
#define RADEON_CLK_PWRMGT_CNTL 0x0014
# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
# define RADEON_MC_BUSY (1 << 16)
# define RADEON_DLL_READY (1 << 19)
# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
| 