From 075ed1d6fd1d58c1f46d556df79f44153f10edd8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Sep 2008 17:27:00 -0400 Subject: radeon: pll and interlace updates from the ddx also some formatting cleanup in radeon_reg.h --- linux-core/radeon_mode.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'linux-core/radeon_mode.h') diff --git a/linux-core/radeon_mode.h b/linux-core/radeon_mode.h index 62672c33..d4b33dd9 100644 --- a/linux-core/radeon_mode.h +++ b/linux-core/radeon_mode.h @@ -137,11 +137,16 @@ struct radeon_tmds_pll { #define RADEON_MAX_BIOS_CONNECTOR 16 -#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) -#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) -#define RADEON_PLL_USE_REF_DIV (1 << 2) -#define RADEON_PLL_LEGACY (1 << 3) -#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) +#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) +#define RADEON_PLL_USE_REF_DIV (1 << 2) +#define RADEON_PLL_LEGACY (1 << 3) +#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) +#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) +#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) +#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) +#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) struct radeon_pll { uint16_t reference_freq; -- cgit v1.2.3