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2007-08-15nouveau: Use count parameter in nouveau_notifier_alloc().Ben Skeggs
2007-08-15nouveau: Turn some messages into DRM_DEBUGs..Ben Skeggs
2007-08-15nouveau: Allow GART notifiers when using sgdma code.Ben Skeggs
2007-08-15nouveau: Workaround mysterious PRAMIN clobbering by the card.Ben Skeggs
2007-08-15nouveau: Catch all NV4x chips instead of just NV_40.Ben Skeggs
2007-08-15nouveau/nv40: Fix channel scheduling.Ben Skeggs
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
2007-08-11i915: i965 non-secure batchbuffer bit has moved.Dave Airlie
2007-08-10nouveau/nv50: demagic instmem setup.Ben Skeggs
2007-08-10nouveau: Allow creation of gpuobjs before any other init has taken place.Ben Skeggs
2007-08-09nouveau: silence irq handler a bitBen Skeggs
2007-08-09nouveau/nv40: add some missing pciids.Ben Skeggs
2007-08-08nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entryMatthieu Castet
This should improve multi fifo
2007-08-08nouveau: Always allocate drm's push buffer in VRAMBen Skeggs
Fixes #11868
2007-08-08nouveau: return channel idBen Skeggs
2007-08-08nouveau/nv50: hack up initial channel context from current stateBen Skeggs
We really should be providing static values like the nv40 PGRAPH code does, however, this will do for now to keep X at least working.
2007-08-08nouveau: enable/disable engine-specific interrupts in _init()/_takedown()Ben Skeggs
All interrupts are still masked by PMC until init is finished.
2007-08-07nouveau : fix enable irq (in the previous code all irq were masked by engineMatthieu Castet
init after irq_postinstall)
2007-08-07nouveau: Init global gpuobj list early, unbreaks sgdma code.Ben Skeggs
2007-08-06nouveau: Bump PCI GART to 16MBStephane Marchesin
2007-08-06nouveau: ouch, add nouveau_dma.[ch] files..Ben Skeggs
2007-08-06nouveau: Remove PGRAPH_SURFACE hack, it wont work now anyway.Ben Skeggs
Need to find another way of doing this, ideally someone'd hunt down which object/method controls it! The Xv blit adaptor is likely now broken on cards that have pNv->WaitVSyncPossible enabled.
2007-08-06nouveau: Give DRM its own gpu channelBen Skeggs
If your card doesn't have working context switching, it is now broken.
2007-08-06nouveau: Determine trapped channel id from active grctx on >=NV40Ben Skeggs
2007-08-06nouveau: Various internal and external API changesBen Skeggs
1. DRM_NOUVEAU_GPUOBJ_FREE Used to free GPU objects. The obvious usage case is for Gr objects, but notifiers can also be destroyed in the same way. GPU objects gain a destructor method and private data fields with this change, so other specialised cases (like notifiers) can be implemented on top of gpuobjs. 2. DRM_NOUVEAU_CHANNEL_FREE 3. DRM_NOUVEAU_CARD_INIT Ideally we'd do init during module load, but this isn't currently possible. Doing init during firstopen() is bad as X has a love of opening/closing the DRM many times during startup. Once the modesetting-101 branch is merged this can go away. IRQs are enabled in nouveau_card_init() now, rather than having the X server call drmCtlInstHandler(). We'll need this for when we give the kernel module its own channel. 4. DRM_NOUVEAU_GETPARAM Add CHIPSET_ID value, which will return the chipset id derived from NV_PMC_BOOT_0. 4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06nouveau: Pass channel struct around instead of channel id.Ben Skeggs
2007-08-03nouveau:nv10: fill and use load,save graph context functionsPatrice Mandin
2007-07-27nouveau: creating notifier in PCI memory for PCIGARTArthur Huillet
2007-07-20Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.Eric Anholt
The data is now in kernel space, copied in/out as appropriate according to the This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal with those failures. This also means that XFree86 4.2.0 support for i810 DRM is lost.
2007-07-20Replace filp in ioctl arguments with drm_file *file_priv.Eric Anholt
As a fallout, replace filp storage with file_priv storage for "unique identifier of a client" all over the DRM. There is a 1:1 mapping, so this should be a noop. This could be a minor performance improvement, as everything on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls went the other direction.
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code.
2007-07-19FreeBSD warnings cleanup.Eric Anholt
2007-07-19Merge branch 'origin'Eric Anholt
2007-07-19nouveau/nv50: get non-default push buffer sizes working.Ben Skeggs
2007-07-18Add dry-coded DRM drawable private information storage for FreeBSD.Eric Anholt
With this, all modules build again.
2007-07-18nouveau: Make nouveau_wait_for_idle() read PTIMER.Pekka Paalanen
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18nouveau: Add read() method to Engine.timer.Pekka Paalanen
This is not called from anywhere, yet.
2007-07-18nouveau: Add bitfield names for NSOURCE and NSTATUS.Pekka Paalanen
Name strings and pretty-printing in nouveau_graph_dump_trap_info().
2007-07-18nouveau: Replace 0x00400104 and 0x00400108 with names.Pekka Paalanen
NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE. The prefix NV03 is chosen because nv10reg.h had no versioned prefix, and the code using these registers does not check card_type.
2007-07-18fix some missing whitespace/tabDave Airlie
2007-07-18drm: remove drm_u64_t, replace with uint64_t everwhereDave Airlie
This might break something, stdint.h inclusion in drm.h maybe required but I'm not sure yet what platforms have it what ones don't.
2007-07-17nouveau: Destroy PGRAPH context table on PGRAPH takedownBen Skeggs
2007-07-17nouveau: G8x PCIEGARTBen Skeggs
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
2007-07-16Correct errors in the usage of pci_map_page.Ian Romanick
With these changes the driver no longer instantly hard-locks a 6600LE on a PowerPC G5. I haven't tested any 3D apps yet.
2007-07-16Fix FreeBSD build.Eric Anholt
2007-07-16drm: remove drm_buf_tDave Airlie
2007-07-16drm: detypedef ttm/bo/fence codeDave Airlie
2007-07-16drm: remove hashtab/sman and object typedefsDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-07-16drm: remove ttm userspace typedefsDave Airlie
2007-07-16drm: detypedef drm.h and fixup all problemsDave Airlie
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 01:16:36 +0000
tate[I810_DEST_SETUP_SIZE]; unsigned int TexState[2][I810_TEX_SETUP_SIZE]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ } drm_i810_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ /* i810 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) #define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) #define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) #define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) #define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) #define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) #define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) #define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) #define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) #define DRM_IOCTL_I810_FLIP DRM_IO ( 0x4e ) typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i810_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i810_vertex_t; typedef struct _drm_i810_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i810_copy_t; #define PR_TRIANGLES (0x0<<18) #define PR_TRISTRIP_0 (0x1<<18) #define PR_TRISTRIP_1 (0x2<<18) #define PR_TRIFAN (0x3<<18) #define PR_POLYGON (0x4<<18) #define PR_LINES (0x5<<18) #define PR_LINESTRIP (0x6<<18) #define PR_RECTS (0x7<<18) #define PR_MASK (0x7<<18) typedef struct drm_i810_dma { void *virtual; int request_idx; int request_size; int granted; } drm_i810_dma_t; typedef struct _drm_i810_overlay_t { unsigned int offset; /* Address of the Overlay Regs */ unsigned int physical; } drm_i810_overlay_t; typedef struct _drm_i810_mc { int idx; /* buffer index */ int used; /* nr bytes in use */ int num_blocks; /* number of GFXBlocks */ int *length; /* List of lengths for GFXBlocks (FUTURE)*/ unsigned int last_render; /* Last Render Request */ } drm_i810_mc_t; #endif /* _I810_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 01:16:36 +0000