renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

Age	Commit message (Collapse)	Author
2005-02-13	Fixed Futex release bug. Bumped driver date and patchlevel.	Thomas Hellstrom

2005-02-10	add support for texture micro tiling on radeon/r200. Add support for r100	Roland Scheidegger
	cube maps (since it also requires a version bump) at the same time.
2005-02-08	Close a race which could allow for privilege escalation by users with DRI	Eric Anholt
	privileges on Radeon hardware. Essentially, a malicious program could submit a packet containing an offset (possibly in main memory) to be rendered from/to, while a separate thread switched that offset in userspace rapidly between a valid value and an invalid one. radeon_check_and_fixup_offset() would pull the offset in from user space, check it, and spit it back out to user space to be copied in later by the emit code. It would sometimes catch the bad value, but sometimes the malicious program could modify it after the check and get an invalid offset rendered from/to. Fix this by allocating a temporary buffer and copying the data in at once. While here, make the cliprects stuff not do the VERIFYAREA_READ and COPY_FROM_USER_UNCHECKED gymnastics, avoiding a lock order reversal on FreeBSD. Performance impact is negligible -- no difference on r200 to ~1% improvement on rv200 in quake3 tests (P4 1Ghz, demofour at 1024x768, n=4 or 5).
2005-02-07	fix agp detection on linux	Dave Airlie

2005-02-05	- Implement drm_initmap, and extend it with the resource number to help	Eric Anholt
	FreeBSD. Add drm_get_resource_{start\|len} so linux-specific stuff doesn't need to be in shared code. - Fix mach64 build by using __DECONST to work around passing a const pointer to useracc, which is unfortunately not marked const. - Get rid of a lot of maplist code by not having dev->maplist be a pointer, and by sticking the link entries directly in drm_local_map_t rather than having a separate structure for the linked list. - Factor out map uninit and removal into its own routine, rather than duplicating in both drm_takedown() and drm_rmmap(). - Hook up more driver functions, and correct FreeBSD-specific bits of radeon_cp.c, making radeon work. - Baby steps towards using bus_space as we should.
2005-02-03	Via driver: Add missing drm_poll function to via driver in core.	Thomas Hellstrom

2005-02-03	Declare r128_do_cleanup_pageflip static since it's only used here and its	Eric Anholt
	prototype went away.
2005-02-03	Cast user data to correct type in radeon_surface_free's copyin.	Eric Anholt

2005-02-01	cleanup patch from Adrian Bunk <bunk@stusta.de>	Dave Airlie

2005-02-01	make functions static in i915, remove unused functions	Dave Airlie

2005-01-27	Fixed multiple devices DMA bug. Fixed PCI path FIRE command detection	Thomas Hellstrom

2005-01-27	fix incorrect PCI id for ATI radeon	Dave Airlie

2005-01-26	(Stephane Marchesin,me) Add radeon framebuffer tiling support to radeon	Roland Scheidegger
	drm. Add new ioctls to manage surfaces which cover the tiled areas
2005-01-26	replace magic number with macro constant RADEON_ZBLOCK16	Roland Scheidegger

2005-01-20	Removed one bogus Savage3D PCI ID. Corrected another one. Restored	Felix Kuehling
	numerical ordering.
2005-01-20	Add a Savage3D PCI ID	Adam Jackson

2005-01-20	Corrected some confusion of vb_stride and vtx_size	Felix Kuehling
	Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX for ELTs support in the _savage_render_stage of the 3D driver Bumped minor version and driver date
2005-01-17	Some code commenting concerning the FIFO & DMA engine.	Jose Fonseca

2005-01-16	This table is in radeon_drv.h along with the version number so remove it	Dave Airlie
	from here
2005-01-16	The patch makes drmAddBufs/drmMapBufs can handle buffers in video memory	Dave Airlie
	The attached patch adds a new buffer type DRM_FB_BUFFER. It works like AGP memory but uses video memory. From: austinyuan@viatech.com.cn (fd.o bug 1668) Signed-off-by: Dave Airlie <airlied@linux.ie>
2005-01-16	Fixed a bug that prevented the driver from ever emitting triangle strips or	Felix Kuehling
	fans. Bumped patchlevel and driver date.
2005-01-15	Setup MTRRs for frame buffer and aperture manually on Savage3D and	Felix Kuehling
	Savage4-based cards. Automatic setup in drm_initmap doesn't work due to the weird alignment and size of the aperture.
2005-01-10	Only try to find the agp_buffer_map if dma_type is AGP. This is all that's	Felix Kuehling
	needed on the DRM side to support PCI Savages. Bumped patch level and driver date.
2005-01-09	Improved workaround for Savage3D DMA lockup to emit NOPs only before the	Felix Kuehling
	first indexed drawing command of a cmdbuf or if a wait command was emitted since the last indexed drawing command.
2005-01-08	Fixed off-by-one error in savage_bci_wait_fifo_shadow.	Felix Kuehling

2005-01-07	via updates: moved the verifier state struct to dev_priv. Implemented AGP	Thomas Hellstrom
	alignment check.
2005-01-07	Updated via DRM with check for stray FIRE commands primitive list.	Thomas Hellstrom

2005-01-06	Add i915GM support Add resume functionality (must be used with later DDX)	Alan Hourihane
	Bump to 1.2
2005-01-06	via DRM: Updated the verifier to check the vertex lists more thorough. This	Thomas Hellstrom
	should hopefully stop it from getting out of sync. The PCI command parser is still not updated.
2005-01-05	3D scissor regs are now managed by the DRM to iterate over clip rects	Felix Kuehling
	passed to the cmdbuf ioctl (try xeyes on top of glxgears ;-) Tightened the texture state check Bumped Savage DRM version to 2.1.0 so that DRI driver can (theoretically) depend on the DRM to manage the scissor registers
2005-01-05	Bumped driver date and minor version.	Thomas Hellstrom

2005-01-05	VIA update:	Thomas Hellstrom
	Release video futexes when context is destroyed (This was previously done by the X server). Added New Unichrome Pro VIDEO DMA commands to the verifier. Added Quiescent heavyweight lock mode.
2005-01-05	Fixed the DMA buffer age test. Should fix occasional "soft" lockups. Bumped	Felix Kuehling
	patch level and driver date.
2005-01-01	Completeley rewritten Savage DRM which can be considered secure (modulo	Felix Kuehling
	implementation errors). Direct hardware (MMIO, BCI) access is no longer needed in the Mesa driver. Bumped version to 2.0.0. Corresponding changes to the DDX and Mesa drivers are being committed.
2005-01-01	Added a new DRM map type _DRM_CONSISTENT for consistent PCI memory. It uses	Felix Kuehling
	drm_pci_alloc/free for allocating/freeing the memory. Only implemented in the Linux DRM so far.
2004-12-31	VIA DRM: verifier: Added verbose palette error reporting, and support for	Thomas Hellstrom
	stipple palettes together with rudimentary checks for texture palette sizes. other: Bumped version patchlevel and driver date.
2004-12-31	VIA DRM: Stability enhancements and cleanups in via_dma.c Added explicit	Thomas Hellstrom
	licence notice in via_dma.c
2004-12-21	via DRM: Tightened the security for some functions of the	Thomas Hellstrom
	DRM_IOCTL_VIA_DMA_INIT IOCTL. Bumped patchlevel and driver date. XFree86 bug: 2119
2004-12-20	Copy HC_ParaType_Auto change to shared-core. Bump version numbers and	Keith Whitwell
	dates.
2004-12-19	via changes: Fixed typecasting bug in via_dma.c, and possible short-circuit	Thomas Hellstrom
	bug in the cmdbuf_size ioctl. Modified ring-buffer jump code AGAIN, due to new oddities discovered on the Unichrome Pro with faster processors. Bumped patchlevel and driver date.
2004-12-13	VIA drm updates:	Thomas Hellstrom
	1. Improved security check of AGP texture adresses. 2. Hopefully last fix of ring-buffer jump oddities. 3. Added ioctl to check available space and command regulator lag in ring-buffer. This is needed for 3D application responsiveness.
2004-12-08	(Stephane Marchesin, me) add hyperz support to radeon drm. Only fast z	Roland Scheidegger
	clear and z buffer compression are working correctly, hierarchical-z is not.
2004-12-06	Security and optimization fixes for the via drm:	Thomas Hellstrom
	1. The command verifier was never initialized in the non-core source tree. 2. Check added that the AGP ring buffer has been initialized before accepting command buffer. 3. Free space check in the AGP buffer is moved to after command verification, which is more optimal in most cases.
2004-12-03	Added 3D functionality to the via command verifier. Modified the via	Thomas Hellstrom
	ring-buffer code somewhat to workaround hardware problems. Bumped via minor version number.
2004-12-03	Make 1-bit fields be unsigned (no sign bit :). sparse complains about them:	Dave Airlie
	drivers/char/drm/sis_ds.h:88:12: warning: dubious one-bit signed bitfield drivers/char/drm/sis_ds.h:89:16: warning: dubious one-bit signed bitfield Signed-off-by: Randy Dunlap <rddunlap@osdl.org> Signed-off-by: Dave Airlie <airlied@linux.ie>
2004-11-27	Reworked PCI MMIO command buffer parser, and imported code from the Mesa	Thomas Hellstrom
	driver. It can now handle the 3D OpenGL commands from the Mesa unichrome driver. Added vsync frequency detection support. This will be used in the future for XvMC and better frame timing. Bumped minor version number and driver date.
2004-11-11	patch from bug 1803 - will try and push to kernel soon	Dave Airlie

2004-11-07	add some more r300 pci ids	Dave Airlie

2004-11-06	Convert more drivers for bsd-core, moving the ioctl definitions to shared	Eric Anholt
	code. Remove the "drv" from sisdrv, as it's unnecessary. Use the drm_pci functions in i915 instead of per-os implementations of the same. Avoid whitespace within fields in drm_pciids.txt (one of the r300 definitions), since it breaks the bsd pciids script. Tested on sis, mga, r128. i915 needs more work.
2004-11-06	Move radeon i2c include to top of file	Jon Smirl

/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- */ /* * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include "drmP.h" #include "drm.h" #include "i915_drm.h" #include "i915_drv.h" /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time * the head pointer changes, so that EBUSY only happens if the ring * actually stalls for (eg) 3 seconds. */ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_ring_buffer_t *ring = &(dev_priv->ring); u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; u32 acthd_reg = IS_I965G(dev) ? I965REG_ACTHD : I915REG_ACTHD; u32 last_acthd = I915_READ(acthd_reg); u32 acthd; int i; for (i = 0; i < 100000; i++) { ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; acthd = I915_READ(acthd_reg); ring->space = ring->head - (ring->tail + 8); if (ring->space < 0) ring->space += ring->Size; if (ring->space >= n) return 0; if (ring->head != last_head) i = 0; if (acthd != last_acthd) i = 0; last_head = ring->head; last_acthd = acthd; msleep_interruptible (10); } return -EBUSY; } void i915_kernel_lost_context(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_ring_buffer_t *ring = &(dev_priv->ring); ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; ring->space = ring->head - (ring->tail + 8); if (ring->space < 0) ring->space += ring->Size; } static int i915_dma_cleanup(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ if (dev->irq) drm_irq_uninstall(dev); if (dev_priv->ring.virtual_start) { drm_core_ioremapfree(&dev_priv->ring.map, dev); dev_priv->ring.virtual_start = 0; dev_priv->ring.map.handle = 0; dev_priv->ring.map.size = 0; } if (dev_priv->status_page_dmah) { drm_pci_free(dev, dev_priv->status_page_dmah); dev_priv->status_page_dmah = NULL; /* Need to rewrite hardware status page */ I915_WRITE(0x02080, 0x1ffff000); } if (dev_priv->status_gfx_addr) { dev_priv->status_gfx_addr = 0; drm_core_ioremapfree(&dev_priv->hws_map, dev); I915_WRITE(0x02080, 0x1ffff000); } return 0; } #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16) #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff) #define DRI2_SAREA_BLOCK_NEXT(p) \ ((void *) ((unsigned char *) (p) + \ DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p))) #define DRI2_SAREA_BLOCK_END 0x0000 #define DRI2_SAREA_BLOCK_LOCK 0x0001 #define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002 static int setup_dri2_sarea(struct drm_device * dev, struct drm_file *file_priv, drm_i915_init_t * init) { drm_i915_private_t *dev_priv = dev->dev_private; int ret; unsigned int *p, *end, *next; mutex_lock(&dev->struct_mutex); dev_priv->sarea_bo = drm_lookup_buffer_object(file_priv, init->sarea_handle, 1); mutex_unlock(&dev->struct_mutex); if (!dev_priv->sarea_bo) { DRM_ERROR("did not find sarea bo\n"); return -EINVAL; } ret = drm_bo_kmap(dev_priv->sarea_bo, 0, dev_priv->sarea_bo->num_pages, &dev_priv->sarea_kmap); if (ret) { DRM_ERROR("could not map sarea bo\n"); return ret; } p = dev_priv->sarea_kmap.virtual; end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT); while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) { switch (DRI2_SAREA_BLOCK_TYPE(*p)) { case DRI2_SAREA_BLOCK_LOCK: dev->lock.hw_lock = (void *) (p + 1); dev->sigdata.lock = dev->lock.hw_lock; break; } next = DRI2_SAREA_BLOCK_NEXT(p); if (next <= p || end < next) { DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n", next, p, end); return -EINVAL; } p = next; } return 0; } static int i915_initialize(struct drm_device * dev, struct drm_file *file_priv, drm_i915_init_t * init) { drm_i915_private_t *dev_priv = dev->dev_private; int ret; dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); i915_dma_cleanup(dev); return -EINVAL; } if (init->mmio_offset != 0) dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio_map) { i915_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); return -EINVAL; } #ifdef I915_HAVE_BUFFER dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS; #endif if (init->sarea_priv_offset) dev_priv->sarea_priv = (drm_i915_sarea_t *) ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); else { /* No sarea_priv for you! */ dev_priv->sarea_priv = NULL; } dev_priv->ring.Start = init->ring_start; dev_priv->ring.End = init->ring_end; dev_priv->ring.Size = init->ring_size; dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->ring.map.offset = init->ring_start; dev_priv->ring.map.size = init->ring_size; dev_priv->ring.map.type = 0; dev_priv->ring.map.flags = 0; dev_priv->ring.map.mtrr = 0; drm_core_ioremap(&dev_priv->ring.map, dev); if (dev_priv->ring.map.handle == NULL) { i915_dma_cleanup(dev); DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); return -ENOMEM; } dev_priv->ring.virtual_start = dev_priv->ring.map.handle; dev_priv->cpp = init->cpp; if (dev_priv->sarea_priv) dev_priv->sarea_priv->pf_current_page = 0; /* We are using separate values as placeholders for mechanisms for * private backbuffer/depthbuffer usage. */ dev_priv->use_mi_batchbuffer_start = 0; if (IS_I965G(dev)) /* 965 doesn't support older method */ dev_priv->use_mi_batchbuffer_start = 1; /* Allow hardware batchbuffers unless told otherwise. */ dev_priv->allow_batchbuffer = 1; /* Enable vblank on pipe A for older X servers */ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A; /* Program Hardware Status Page */ if (!I915_NEED_GFX_HWS(dev)) { dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); if (!dev_priv->status_page_dmah) { i915_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; memset(dev_priv->hw_status_page, 0, PAGE_SIZE); I915_WRITE(0x02080, dev_priv->dma_status_page); } DRM_DEBUG("Enabled hardware status page\n"); #ifdef I915_HAVE_BUFFER mutex_init(&dev_priv->cmdbuf_mutex); #endif if (init->func == I915_INIT_DMA2) { ret = setup_dri2_sarea(dev, file_priv, init); if (ret) { i915_dma_cleanup(dev); DRM_ERROR("could not set up dri2 sarea\n"); return ret; } } return 0; } static int i915_dma_resume(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; DRM_DEBUG("\n"); if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); return -EINVAL; } if (!dev_priv->mmio_map) { DRM_ERROR("can not find mmio map!\n"); return -EINVAL; } if (dev_priv->ring.map.handle == NULL) { DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); return -ENOMEM; } /* Program Hardware Status Page */ if (!dev_priv->hw_status_page) { DRM_ERROR("Can not find hardware status page\n"); return -EINVAL; } DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); if (dev_priv->status_gfx_addr != 0) I915_WRITE(0x02080, dev_priv->status_gfx_addr); else I915_WRITE(0x02080, dev_priv->dma_status_page); DRM_DEBUG("Enabled hardware status page\n"); return 0; } static int i915_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_i915_init_t *init = data; int retcode = 0; switch (init->func) { case I915_INIT_DMA: case I915_INIT_DMA2: retcode = i915_initialize(dev, file_priv, init); break; case I915_CLEANUP_DMA: retcode = i915_dma_cleanup(dev); break; case I915_RESUME_DMA: retcode = i915_dma_resume(dev); break; default: retcode = -EINVAL; break; } return retcode; } /* Implement basically the same security restrictions as hardware does * for MI_BATCH_NON_SECURE. These can be made stricter at any time. * * Most of the calculations below involve calculating the size of a * particular instruction. It's important to get the size right as * that tells us where the next instruction to check is. Any illegal * instruction detected will be given a size of zero, which is a * signal to abort the rest of the buffer. */ static int do_validate_cmd(int cmd) { switch (((cmd >> 29) & 0x7)) { case 0x0: switch ((cmd >> 23) & 0x3f) { case 0x0: return 1; /* MI_NOOP */ case 0x4: return 1; /* MI_FLUSH */ default: return 0; /* disallow everything else */ } break; case 0x1: return 0; /* reserved */ case 0x2: return (cmd & 0xff) + 2; /* 2d commands */ case 0x3: if (((cmd >> 24) & 0x1f) <= 0x18) return 1; switch ((cmd >> 24) & 0x1f) { case 0x1c: return 1; case 0x1d: switch ((cmd >> 16) & 0xff) { case 0x3: return (cmd & 0x1f) + 2; case 0x4: return (cmd & 0xf) + 2; default: return (cmd & 0xffff) + 2; } case 0x1e: if (cmd & (1 << 23)) return (cmd & 0xffff) + 1; else return 1; case 0x1f: if ((cmd & (1 << 23)) == 0) /* inline vertices */ return (cmd & 0x1ffff) + 2; else if (cmd & (1 << 17)) /* indirect random */ if ((cmd & 0xffff) == 0) return 0; /* unknown length, too hard */ else return (((cmd & 0xffff) + 1) / 2) + 1; else return 2; /* indirect sequential */ default: return 0; } default: return 0; } return 0; } static int validate_cmd(int cmd) { int ret = do_validate_cmd(cmd); /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ return ret; } static int i915_emit_cmds(struct drm_device *dev, int __user *buffer, int dwords) { drm_i915_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) return -EINVAL; BEGIN_LP_RING((dwords+1)&~1); for (i = 0; i < dwords;) { int cmd, sz; if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) return -EINVAL; if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) return -EINVAL; OUT_RING(cmd); while (++i, --sz) { if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) { return -EINVAL; } OUT_RING(cmd); } } if (dwords & 1) OUT_RING(0); ADVANCE_LP_RING(); return 0; } int i915_emit_box(struct drm_device * dev, struct drm_clip_rect __user * boxes, int i, int DR1, int DR4) { drm_i915_private_t *dev_priv = dev->dev_private; struct drm_clip_rect box; RING_LOCALS; if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { return -EFAULT; } if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { DRM_ERROR("Bad box %d,%d..%d,%d\n", box.x1, box.y1, box.x2, box.y2); return -EINVAL; } if (IS_I965G(dev)) { BEGIN_LP_RING(4); OUT_RING(GFX_OP_DRAWRECT_INFO_I965); OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); OUT_RING(DR4); ADVANCE_LP_RING(); } else { BEGIN_LP_RING(6); OUT_RING(GFX_OP_DRAWRECT_INFO); OUT_RING(DR1); OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); OUT_RING(DR4); OUT_RING(0); ADVANCE_LP_RING(); } return 0; } /* XXX: Emitting the counter should really be moved to part of the IRQ * emit. For now, do it in both places: */ void i915_emit_breadcrumb(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; RING_LOCALS; if (++dev_priv->counter > BREADCRUMB_MASK) { dev_priv->counter = 1; DRM_DEBUG("Breadcrumb counter wrapped around\n"); } if (dev_priv->sarea_priv) dev_priv->sarea_priv->last_enqueue = dev_priv->counter; BEGIN_LP_RING(4); OUT_RING(CMD_STORE_DWORD_IDX); OUT_RING(20); OUT_RING(dev_priv->counter); OUT_RING(0); ADVANCE_LP_RING(); } int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush) { drm_i915_private_t *dev_priv = dev->dev_private; uint32_t flush_cmd = CMD_MI_FLUSH; RING_LOCALS; flush_cmd |= flush; i915_kernel_lost_context(dev); BEGIN_LP_RING(4); OUT_RING(flush_cmd); OUT_RING(0); OUT_RING(0); OUT_RING(0); ADVANCE_LP_RING(); return 0; } static int i915_dispatch_cmdbuffer(struct drm_device * dev, drm_i915_cmdbuffer_t * cmd) { #ifdef I915_HAVE_FENCE drm_i915_private_t *dev_priv = dev->dev_private; #endif int nbox = cmd->num_cliprects; int i = 0, count, ret; if (cmd->sz & 0x3) { DRM_ERROR("alignment\n"); return -EINVAL; } i915_kernel_lost_context(dev); count = nbox ? nbox : 1; for (i = 0; i < count; i++) { if (i < nbox) { ret = i915_emit_box(dev, cmd->cliprects, i, cmd->DR1, cmd->DR4); if (ret) return ret; } ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); if (ret) return ret; } i915_emit_breadcrumb(dev); #ifdef I915_HAVE_FENCE if (unlikely((dev_priv->counter & 0xFF) == 0)) drm_fence_flush_old(dev, 0, dev_priv->counter); #endif return 0; } int i915_dispatch_batchbuffer(struct drm_device * dev, drm_i915_batchbuffer_t * batch) { drm_i915_private_t *dev_priv = dev->dev_private; struct drm_clip_rect __user *boxes = batch->cliprects; int nbox = batch->num_cliprects; int i = 0, count; RING_LOCALS; if ((batch->start | batch->used) & 0x7) { DRM_ERROR("alignment\n"); return -EINVAL; } i915_kernel_lost_context(dev); count = nbox ? nbox : 1; for (i = 0; i < count; i++) { if (i < nbox) { int ret = i915_emit_box(dev, boxes, i, batch->DR1, batch->DR4); if (ret) return ret; } if (dev_priv->use_mi_batchbuffer_start) { BEGIN_LP_RING(2); if (IS_I965G(dev)) { OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); OUT_RING(batch->start); } else { OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); OUT_RING(batch->start | MI_BATCH_NON_SECURE); } ADVANCE_LP_RING(); } else { BEGIN_LP_RING(4); OUT_RING(MI_BATCH_BUFFER); OUT_RING(batch->start | MI_BATCH_NON_SECURE); OUT_RING(batch->start + batch->used - 4); OUT_RING(0); ADVANCE_LP_RING(); } } i915_emit_breadcrumb(dev); #ifdef I915_HAVE_FENCE if (unlikely((dev_priv->counter & 0xFF) == 0)) drm_fence_flush_old(dev, 0, dev_priv->counter); #endif return 0; } static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync) { drm_i915_private_t *dev_priv = dev->dev_private; u32 num_pages, current_page, next_page, dspbase; int shift = 2 * plane, x, y; RING_LOCALS; /* Calculate display base offset */ num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3; next_page = (current_page + 1) % num_pages; switch (next_page) { default: case 0: dspbase = dev_priv->sarea_priv->front_offset; break; case 1: dspbase = dev_priv->sarea_priv->back_offset; break; case 2: dspbase = dev_priv->sarea_priv->third_offset; break; } if (plane == 0) { x = dev_priv->sarea_priv->planeA_x; y = dev_priv->sarea_priv->planeA_y; } else { x = dev_priv->sarea_priv->planeB_x; y = dev_priv->sarea_priv->planeB_y; } dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp; DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page, dspbase); BEGIN_LP_RING(4); OUT_RING(sync ? 0 : (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP : MI_WAIT_FOR_PLANE_A_FLIP))); OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) | (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));