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path: root/shared-core/nouveau_fifo.c
AgeCommit message (Expand)Author
2007-03-23nouveau: remove unused cruftBen Skeggs
2007-03-21nouveau: support multiple channels per client (breaks drm interface)Ben Skeggs
2007-03-13nouveau: make sure cmdbuf object gets destroyedBen Skeggs
2007-03-13nouveau: associate all created objects with a channel + cleanupsBen Skeggs
2007-03-11nouveau: PUT,GET, not 2xPUTPatrice Mandin
2007-02-28nouveau: intrusive drm interface changesBen Skeggs
2007-02-14nouveau: fix the build on big endian (thanks CyberFoxx)Stephane Marchesin
2007-02-06nouveau: more work on the nv04 context switch code.Stephane Marchesin
2007-02-03nouveau: and of course, I was missing the last nv04 piece.Stephane Marchesin
2007-02-03nouveau: rename registers to their proper names.Stephane Marchesin
2007-01-25nouveau: simplify and fix BIG_ENDIAN flagsPatrice Mandin
2007-01-18nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.Jeremy Kolb
2007-01-17nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.Jeremy Kolb
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
2007-01-13nouveau: first step to make graph ctx worksMatthieu Castet
2007-01-12nouveau : remove useless init : we clear RAMIN beforeMatthieu Castet
2007-01-12nouveau: get nv30 context switching to work.Jeremy Kolb
2007-01-08nouveau: avoid allocating vram that's used as instance memory.Ben Skeggs
2007-01-05Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/Matthieu Castet
2007-01-05Add basic pgraph context for nv10.Matthieu Castet
2007-01-05Cleanup the nv04 fifo code a bit.Stephane Marchesin
2007-01-02nouveau: oops, forgot to free RAMIN..Ben Skeggs
2007-01-02nouveau: Hook up grctx code for NV4x.Ben Skeggs
2007-01-02nouveau: Only clobber PFIFO if no channels are already alloc'dBen Skeggs
2006-12-26nouveau: Alloc cmdbuf for each channel individuallyBen Skeggs
2006-12-21nouveau: save/restore endianness flag on FIFO switchBen Skeggs
2006-12-12Port remaining NV4 RAMIN access from the ddx into the drm.Ben Skeggs
2006-12-03Merge the pciid work.Stephane Marchesin
2006-11-30Use nouveau_mem.c to allocate RAMIN.Ben Skeggs
2006-11-30Wrap access to objects in RAMIN.Ben Skeggs
2006-11-28For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.Matthieu Castet
2006-11-18Only return FIFO number if the FIFO is marked as in use..Ben Skeggs
2006-11-18Check some return vals, fixes a couple of oopses.Ben Skeggs
2006-11-17Dump some useful info when a PGRAPH error occurs.Ben Skeggs
2006-11-14Completely untested NV10/20/30 FIFO context switching changes.Ben Skeggs
2006-11-14Restructure initialisation a bit.Ben Skeggs
2006-11-14Hack around yet another "X restart borkage without nouveau.ko reload" problem.Ben Skeggs
2006-11-06fixup fifo size so it is page alignedDave Airlie
2006-10-18Remove hack which delays activation of a additional channel. The previously ...Ben Skeggs
2006-10-17NV40: *Now* fifo ctx switching works for me..Ben Skeggs
2006-10-17NV40: FIFO context switching now WorksForMe(tm)Ben Skeggs
2006-10-17Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ...Ben Skeggs
2006-10-14Again more work on context switches. They work, sometimes. And when they do t...Stephane Marchesin
2006-10-14Add the missing breaks.Stephane Marchesin
2006-10-13Fix the fifo context size on nv10, nv20 and nv30.Stephane Marchesin
2006-10-14Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals)...Ben Skeggs
2006-10-12Still more work on the context switching code.Stephane Marchesin
2006-10-12More work on the context switch code. Still doesn't work. I'm mostly convince...Stephane Marchesin
2006-10-11Context switching work.Stephane Marchesin
2006-09-07Fix second start of X server without module reload beforehand, and a couple o...Ben Skeggs
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-13 05:55:48 +0000
hl com"> */ #include "drmP.h" #include "sis_drm.h" #include "sis_drv.h" #if defined(__linux__) #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) #include <video/sisfb.h> #else #include <linux/sisfb.h> #endif #endif #define VIDEO_TYPE 0 #define AGP_TYPE 1 #define SIS_MM_ALIGN_SHIFT 4 #define SIS_MM_ALIGN_MASK ( (1 << SIS_MM_ALIGN_SHIFT) - 1) #if defined(__linux__) && defined(CONFIG_FB_SIS) /* fb management via fb device */ #define SIS_MM_ALIGN_SHIFT 0 #define SIS_MM_ALIGN_MASK 0 static void *sis_sman_mm_allocate(void *private, unsigned long size, unsigned alignment) { struct sis_memreq req; req.size = size; sis_malloc(&req); if (req.size == 0) return NULL; else return (void *)~req.offset; } static void sis_sman_mm_free(void *private, void *ref) { sis_free(~((unsigned long)ref)); } static void sis_sman_mm_destroy(void *private) { ; } unsigned long sis_sman_mm_offset(void *private, void *ref) { return ~((unsigned long)ref); } #endif static int sis_fb_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_fb_t fb; int ret; DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *) data, sizeof(fb)); mutex_lock(&dev->struct_mutex); #if defined(__linux__) && defined(CONFIG_FB_SIS) { drm_sman_mm_t sman_mm; sman_mm.private = (void *)0xFFFFFFFF; sman_mm.allocate = sis_sman_mm_allocate; sman_mm.free = sis_sman_mm_free; sman_mm.destroy = sis_sman_mm_destroy; sman_mm.offset = sis_sman_mm_offset; ret = drm_sman_set_manager(&dev_priv->sman, VIDEO_TYPE, &sman_mm); } #else ret = drm_sman_set_range(&dev_priv->sman, VIDEO_TYPE, 0, fb.size >> SIS_MM_ALIGN_SHIFT); #endif if (ret) { DRM_ERROR("VRAM memory manager initialisation error\n"); mutex_unlock(&dev->struct_mutex); return ret; } dev_priv->vram_initialized = 1; dev_priv->vram_offset = fb.offset; mutex_unlock(&dev->struct_mutex); DRM_DEBUG("offset = %u, size = %u", fb.offset, fb.size); return 0; } static int sis_drm_alloc(drm_device_t * dev, drm_file_t * priv, unsigned long data, int pool) { drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_mem_t __user *argp = (drm_sis_mem_t __user *) data; drm_sis_mem_t mem; int retval = 0; drm_memblock_item_t *item; DRM_COPY_FROM_USER_IOCTL(mem, argp, sizeof(mem)); mutex_lock(&dev->struct_mutex); if (0 == ((pool == 0) ? dev_priv->vram_initialized : dev_priv->agp_initialized)) { DRM_ERROR ("Attempt to allocate from uninitialized memory manager.\n"); return DRM_ERR(EINVAL); } mem.size = (mem.size + SIS_MM_ALIGN_MASK) >> SIS_MM_ALIGN_SHIFT; item = drm_sman_alloc(&dev_priv->sman, pool, mem.size, 0, (unsigned long)priv); mutex_unlock(&dev->struct_mutex); if (item) { mem.offset = ((pool == 0) ? dev_priv->vram_offset : dev_priv->agp_offset) + (item->mm-> offset(item->mm, item->mm_info) << SIS_MM_ALIGN_SHIFT); mem.free = item->user_hash.key; mem.size = mem.size << SIS_MM_ALIGN_SHIFT; } else { mem.offset = 0; mem.size = 0; mem.free = 0; retval = DRM_ERR(ENOMEM); } DRM_COPY_TO_USER_IOCTL(argp, mem, sizeof(mem)); DRM_DEBUG("alloc %d, size = %d, offset = %d\n", pool, mem.size, mem.offset); return retval; } static int sis_drm_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_mem_t mem; int ret; DRM_COPY_FROM_USER_IOCTL(mem, (drm_sis_mem_t __user *) data, sizeof(mem)); mutex_lock(&dev->struct_mutex); ret = drm_sman_free_key(&dev_priv->sman, mem.free); mutex_unlock(&dev->struct_mutex); DRM_DEBUG("free = 0x%lx\n", mem.free); return ret; } static int sis_fb_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; return sis_drm_alloc(dev, priv, data, VIDEO_TYPE); } static int sis_ioctl_agp_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_agp_t agp; int ret; dev_priv = dev->dev_private; DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data, sizeof(agp)); mutex_lock(&dev->struct_mutex); ret = drm_sman_set_range(&dev_priv->sman, AGP_TYPE, 0, agp.size >> SIS_MM_ALIGN_SHIFT); if (ret) { DRM_ERROR("AGP memory manager initialisation error\n"); mutex_unlock(&dev->struct_mutex); return ret; } dev_priv->agp_initialized = 1; dev_priv->agp_offset = agp.offset; mutex_unlock(&dev->struct_mutex); DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size); return 0; } static int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; return sis_drm_alloc(dev, priv, data, AGP_TYPE); } static drm_local_map_t *sis_reg_init(drm_device_t *dev) { drm_map_list_t *entry; drm_local_map_t *map; list_for_each_entry(entry, &dev->maplist->head, head) { map = entry->map; if (!map) continue; if (map->type == _DRM_REGISTERS) { return map; } } return NULL; } int sis_idle(drm_device_t *dev) { drm_sis_private_t *dev_priv = dev->dev_private; uint32_t idle_reg; unsigned long end; int i; if (dev_priv->idle_fault) return 0; if (dev_priv->mmio == NULL) { dev_priv->mmio = sis_reg_init(dev); if (dev_priv->mmio == NULL) { DRM_ERROR("Could not find register map.\n"); return 0; } } /* * Implement a device switch here if needed */ if (dev_priv->chipset != SIS_CHIP_315) return 0; /* * Timeout after 3 seconds. We cannot use DRM_WAIT_ON here * because its polling frequency is too low. */ end = jiffies + (DRM_HZ * 3); for (i=0; i<4; ++i) { do { idle_reg = SIS_READ(0x85cc); } while ( !time_after_eq(jiffies, end) && ((idle_reg & 0x80000000) != 0x80000000)); } if (time_after_eq(jiffies, end)) { DRM_ERROR("Graphics engine idle timeout. " "Disabling idle check\n"); dev_priv->idle_fault = 1; } /* * The caller never sees an error code. It gets trapped * in libdrm. */ return 0; } void sis_lastclose(struct drm_device *dev) { drm_sis_private_t *dev_priv = dev->dev_private; if (!dev_priv) return; mutex_lock(&dev->struct_mutex); drm_sman_cleanup(&dev_priv->sman); dev_priv->vram_initialized = 0; dev_priv->agp_initialized = 0; dev_priv->mmio = NULL; mutex_unlock(&dev->struct_mutex); } void sis_reclaim_buffers_locked(drm_device_t * dev, struct file *filp) { drm_sis_private_t *dev_priv = dev->dev_private; drm_file_t *priv = filp->private_data; mutex_lock(&dev->struct_mutex); if (drm_sman_owner_clean(&dev_priv->sman, (unsigned long)priv)) { mutex_unlock(&dev->struct_mutex); return; } if (dev->driver->dma_quiescent) { dev->driver->dma_quiescent(dev); } drm_sman_owner_cleanup(&dev_priv->sman, (unsigned long)priv); mutex_unlock(&dev->struct_mutex); return; } drm_ioctl_desc_t sis_ioctls[] = { [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_drm_free, DRM_AUTH}, [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_drm_free, DRM_AUTH}, [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = {sis_fb_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY} }; int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls);
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-13 05:55:48 +0000