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2003-04-22Move the excitingly named DRM(flush_block_and_flush) and friends toKeith Whitwell
gamma-specific code. Fix templates so i8x0 drivers don't have to define __HAVE_DMA_WAITLIST.
2003-04-22remove unused __HAVE_KERNEL_CTX_SWITCH codeKeith Whitwell
2003-04-22Move a chunk of gamma-specific code out of drm_dma.h. Remove unusedKeith Whitwell
'DRM_FLAG_NOCTX' option.
2003-04-22remove unused dma histogram codeKeith Whitwell
2003-04-22Move a bunch of gamma-specific code into a gamma-specific file. Restore theKeith Whitwell
kooky DRM(write_string) code for gamma.
2003-04-22remove DRM read, poll and write_stringKeith Whitwell
2003-04-21Check for NULL map before calling DRM(ioremapfree) on cleanup. Prevents anLeif Delgass
oops if a map wasn't found (e.g. XFree86 Bugzilla #108)
2003-04-17Add a Kconfig file as used in recent 2.5.x kernels.David Dawes
2003-04-17Make Config.in look more like a recent 2.4.x kernel version.David Dawes
2003-04-17Rework the Linux drm kernel module build to leverage off the standardDavid Dawes
kernel build system. This is based on suggestions and examples from David Woodhouse. This approach has the advantage that the build requirements of a wider range of standard kernels are now supported transparently, but the disadvantage of some extra complexity to handle building against clean vendor-distributed kernel source trees. This has been tested with some recent Red Hat and SuSE distributions.
2003-04-17Bring some drm module changes over from the XFree86 trunk:David Dawes
- Reset 'bound' flag for an agp entry after undbind succeeded in drm_agpsupport.h (Egbert Eich). - Ignore hw_lock for drm device if lock was set by a different instance (ie Xserver) to prevent second server from spinning in driver release function (currently only relevant for i8xx drm drivers) (David Dawes). - Use the agpgart "key" for the unique handle for bindings rather than the memory address (the key is guaranteed to be unique) (David Dawes).
2003-04-17Fix DRM module build on 2.5.41 and later kernels (tqueue -> workqueue).David Dawes
2003-04-08Use list_entry() to get container struct from struct list_head pointers.Leif Delgass
Build fix for RedHat 9 kernel (5 args to remap_page_range()).
2003-04-05add 'SG' map type identifier string (pci scatter/gather) to /proc vm infoLeif Delgass
2003-03-31Warning fix (use %p format for filp)Leif Delgass
2003-03-30Spelling fixes in comments.Eric Anholt
Submitted by: Linus Torvalds <torvalds@transmeta.com>
2003-03-28merged drm-filp-0-1-branchKeith Whitwell
2003-03-26Add 2nd arg for DRM_FREEKeith Whitwell
2003-03-25linux merge for drmAlan Hourihane
2003-03-25XFree86 4.3.0 mergeAlan Hourihane
2003-03-04DRM_FREE/2 patch from Philip BrownKeith Whitwell
2003-02-28Update object targetsLeif Delgass
2003-02-21Merge from bsd-4-0-0-branch.Eric Anholt
2003-02-04disable strict aliasing for building the DRMMichel Daenzer
2003-02-02don't inflate relative vblank sequence numbers on repeated calls (e.g. whenMichel Daenzer
interrupted by a signal)
2003-01-11limit number of pending vblank signals to 100 to prevent DoS, and minorMichel Daenzer
cleanups
2002-12-12enums should be intsDavid Dawes
2002-12-12bring in jantorial changes from 2.5.51Keith Whitwell
2002-12-11remove agpgart informationalKeith Whitwell
2002-12-04further vertical blank interrupt cleanups: remove unused variable,Michel Daenzer
non-ambiguous variable names, don't express subtraction in unnecessarily complicated ways
2002-12-03vertical blank interrupt cleanups: use spinlock instead of semaphore, sendMichel Daenzer
signal directly from interrupt handler instead of using a taskqueue (based on feedback by Linus Torvalds)
2002-11-30vertical blank ioctl can send signal instead of blockingMichel Daenzer
2002-10-30Kernel support for vblank syncing on Rage 128 and Matrox.Eric Anholt
2002-10-29updated e-mail addresses for Keith, Alan and JensJens Owen
2002-10-29preserve CRTC{,2}_OFFSET_CNTL in 2D driver to avoid bad effects whenMichel Daenzer
pageflipping after a mode switch take current page into account in AdjustFrame(); writing the CRTC offset via the CP was probably a bad idea as this can happen asynchronously, reverted take frame offset into account when flipping pages handle CRTC2 as well for pageflipping (untested) preserve GEN_INT_CNTL on mode switches to prevent interrupts from getting disabled
2002-10-22final part of XFree86 4.2.99.2 mergeAlan Hourihane
2002-10-22Import of XFree86 4.2.99.2Alan Hourihane
2002-10-09replaced max() macro with conditional expressionBrian Paul
2002-10-08Fix error condition...Keith Whitwell
2002-10-08Call pci_enable_device() in DRM(irq_busid).Keith Whitwell
2002-09-29Move os-dependent stuff out of radeon_irq.cKeith Whitwell
2002-09-29add support for 16K and 64K page sizes (Bjorn Helgaas)Michel Daenzer
2002-09-26DRM(vblank_wait) is driver specificMichel Daenzer
2002-09-25common ioctl to wait for vertical blank IRQsMichel Daenzer
2002-09-23merged r200-0-2-branch to trunkKeith Whitwell
2002-09-21make sure we never oops because the hardware lock pointer in the sigdataMichel Daenzer
structure is out of date
2002-09-11- Fix various bugs in the DRI support for the i830 and i845G (KeithDavid Dawes
Whitwell). - Major rework of the 2D i830/i845G support, including: - Improve VESA mode selection, and fix refresh rate selection. - Don't duplicate functions provided in the vbe modules. - Don't duplicate functions provided in the vgahw module. - Rewrite memory allocation. - Rewrite initialisation and save/restore state handling. - Decouple the i810 support from i830 and later. - Remove various unnecessary hacks and workarounds. - Fix an 845G problem with the ring buffer not in pre-allocated memory. - Fix screen blanking. - Fix some HW cursor glitches, and turn HW cursor off at VT switch and exit. - Don't attempt to use the i830's function 1 entity. - Fix problems with option handling. (David Dawes). - Add mode VBE-aware mode handling functions to the vbe module (David Dawes).
2002-08-29standardize use of __FUNCTION__ (Linus)Keith Whitwell
2002-08-22Don't (re)define vmalloc_to_page for kernel >= 2.4.19, as it has beenLeif Delgass
backported from 2.5.x. Also fix a couple of incorrect LINUX_VERSION_CODE tests and fix header dependency for r128, radeon when building without AGP.
2002-08-22SetPageLocked only defined in 2.5.x (x=?), use LockPage for 2.4.x (x>=9).Leif Delgass
Also apply build fixes from i810_dma.c to i830_dma.c
an class="hl com"> * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "drmP.h" #include "drm.h" #include "nouveau_drm.h" #include "nouveau_drv.h" static void nv10_praph_pipe(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; nouveau_wait_for_idle(dev); /* XXX check haiku comments */ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200); for (i = 0; i < 48; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000); NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400); for (i = 0; i < 211; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800); for (i = 0; i < 162; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 25; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); for (i = 0; i < 35; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400); for (i = 0; i < 48; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800); for (i = 0; i < 48; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400); for (i = 0; i < 32; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000); for (i = 0; i < 16; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); for (i = 0; i < 4; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); } /* TODO replace address with name use loops */ static int nv10_graph_ctx_regs [] = { NV03_PGRAPH_XY_LOGIC_MISC0, //NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash NV10_PGRAPH_CTX_SWITCH2, NV10_PGRAPH_CTX_SWITCH3, NV10_PGRAPH_CTX_SWITCH4, NV10_PGRAPH_CTX_SWITCH5, NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 0x00400164, 0x00400184, 0x004001a4, 0x004001c4, 0x004001e4, 0x00400168, 0x00400188, 0x004001a8, 0x004001c8, 0x004001e8, 0x0040016c, 0x0040018c, 0x004001ac, 0x004001cc, 0x004001ec, 0x00400170, 0x00400190, 0x004001b0, 0x004001d0, 0x004001f0, 0x00400174, 0x00400194, 0x004001b4, 0x004001d4, 0x004001f4, 0x00400178, 0x00400198, 0x004001b8, 0x004001d8, 0x004001f8, 0x0040017c, 0x0040019c, 0x004001bc, 0x004001dc, 0x004001fc, NV10_PGRAPH_CTX_USER, NV04_PGRAPH_DMA_START_0, NV04_PGRAPH_DMA_START_1, NV04_PGRAPH_DMA_LENGTH, NV04_PGRAPH_DMA_MISC, NV10_PGRAPH_DMA_PITCH, NV04_PGRAPH_BOFFSET0, NV04_PGRAPH_BBASE0, NV04_PGRAPH_BLIMIT0, NV04_PGRAPH_BOFFSET1, NV04_PGRAPH_BBASE1, NV04_PGRAPH_BLIMIT1, NV04_PGRAPH_BOFFSET2, NV04_PGRAPH_BBASE2, NV04_PGRAPH_BLIMIT2, NV04_PGRAPH_BOFFSET3, NV04_PGRAPH_BBASE3, NV04_PGRAPH_BLIMIT3, NV04_PGRAPH_BOFFSET4, NV04_PGRAPH_BBASE4, NV04_PGRAPH_BLIMIT4, NV04_PGRAPH_BOFFSET5, NV04_PGRAPH_BBASE5, NV04_PGRAPH_BLIMIT5, NV04_PGRAPH_BPITCH0, NV04_PGRAPH_BPITCH1, NV04_PGRAPH_BPITCH2, NV04_PGRAPH_BPITCH3, NV04_PGRAPH_BPITCH4, NV10_PGRAPH_SURFACE, NV10_PGRAPH_STATE, NV04_PGRAPH_BSWIZZLE2, NV04_PGRAPH_BSWIZZLE5, NV04_PGRAPH_BPIXEL, NV10_PGRAPH_NOTIFY, NV04_PGRAPH_PATT_COLOR0, NV04_PGRAPH_PATT_COLOR1, NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ 0x00400904, 0x00400908, 0x0040090c, 0x00400910, 0x00400914, 0x00400918, 0x0040091c, 0x00400920, 0x00400924, 0x00400928, 0x0040092c, 0x00400930, 0x00400934, 0x00400938, 0x0040093c, 0x00400940, 0x00400944, 0x00400948, 0x0040094c, 0x00400950, 0x00400954, 0x00400958, 0x0040095c, 0x00400960, 0x00400964, 0x00400968, 0x0040096c, 0x00400970, 0x00400974, 0x00400978, 0x0040097c, 0x00400980, 0x00400984, 0x00400988, 0x0040098c, 0x00400990, 0x00400994, 0x00400998, 0x0040099c, 0x004009a0, 0x004009a4, 0x004009a8, 0x004009ac, 0x004009b0, 0x004009b4, 0x004009b8, 0x004009bc, 0x004009c0, 0x004009c4, 0x004009c8, 0x004009cc, 0x004009d0, 0x004009d4, 0x004009d8, 0x004009dc, 0x004009e0, 0x004009e4, 0x004009e8, 0x004009ec, 0x004009f0, 0x004009f4, 0x004009f8, 0x004009fc, NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ 0x0040080c, NV04_PGRAPH_PATTERN_SHAPE, NV03_PGRAPH_MONO_COLOR0, NV04_PGRAPH_ROP3, NV04_PGRAPH_CHROMA, NV04_PGRAPH_BETA_AND, NV04_PGRAPH_BETA_PREMULT, 0x00400e70, 0x00400e74, 0x00400e78, 0x00400e7c, 0x00400e80, 0x00400e84, 0x00400e88, 0x00400e8c, 0x00400ea0, 0x00400ea4, 0x00400ea8, 0x00400e90, 0x00400e94, 0x00400e98, 0x00400e9c, NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */ NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ 0x00400f04, 0x00400f24, 0x00400f08, 0x00400f28, 0x00400f0c, 0x00400f2c, 0x00400f10, 0x00400f30, 0x00400f14, 0x00400f34, 0x00400f18, 0x00400f38, 0x00400f1c, 0x00400f3c, NV10_PGRAPH_XFMODE0, NV10_PGRAPH_XFMODE1, NV10_PGRAPH_GLOBALSTATE0, NV10_PGRAPH_GLOBALSTATE1, NV04_PGRAPH_STORED_FMT, NV04_PGRAPH_SOURCE_COLOR, NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ 0x00400404, 0x00400484, 0x00400408, 0x00400488, 0x0040040c, 0x0040048c, 0x00400410, 0x00400490, 0x00400414, 0x00400494, 0x00400418, 0x00400498, 0x0040041c, 0x0040049c, 0x00400420, 0x004004a0, 0x00400424, 0x004004a4, 0x00400428, 0x004004a8, 0x0040042c, 0x004004ac, 0x00400430, 0x004004b0, 0x00400434, 0x004004b4, 0x00400438, 0x004004b8, 0x0040043c, 0x004004bc, 0x00400440, 0x004004c0, 0x00400444, 0x004004c4, 0x00400448, 0x004004c8, 0x0040044c, 0x004004cc, 0x00400450, 0x004004d0, 0x00400454, 0x004004d4, 0x00400458, 0x004004d8, 0x0040045c, 0x004004dc, 0x00400460, 0x004004e0, 0x00400464, 0x004004e4, 0x00400468, 0x004004e8, 0x0040046c, 0x004004ec, 0x00400470, 0x004004f0, 0x00400474, 0x004004f4, 0x00400478, 0x004004f8, 0x0040047c, 0x004004fc, NV03_PGRAPH_ABS_UCLIP_XMIN, NV03_PGRAPH_ABS_UCLIP_XMAX, NV03_PGRAPH_ABS_UCLIP_YMIN, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x00400550, 0x00400558, 0x00400554, 0x0040055c, NV03_PGRAPH_ABS_UCLIPA_XMIN, NV03_PGRAPH_ABS_UCLIPA_XMAX, NV03_PGRAPH_ABS_UCLIPA_YMIN, NV03_PGRAPH_ABS_UCLIPA_YMAX, NV03_PGRAPH_ABS_ICLIP_XMAX, NV03_PGRAPH_ABS_ICLIP_YMAX, NV03_PGRAPH_XY_LOGIC_MISC1, NV03_PGRAPH_XY_LOGIC_MISC2, NV03_PGRAPH_XY_LOGIC_MISC3, NV03_PGRAPH_CLIPX_0, NV03_PGRAPH_CLIPX_1, NV03_PGRAPH_CLIPY_0, NV03_PGRAPH_CLIPY_1, 0x00400e40, 0x00400e44, 0x00400e48, 0x00400e4c, 0x00400e50, 0x00400e54, 0x00400e58, 0x00400e5c, 0x00400e60, 0x00400e64, 0x00400e68, 0x00400e6c, 0x00400e00, 0x00400e04, 0x00400e08, 0x00400e0c, 0x00400e10, 0x00400e14, 0x00400e18, 0x00400e1c, 0x00400e20, 0x00400e24, 0x00400e28, 0x00400e2c, 0x00400e30, 0x00400e34, 0x00400e38, 0x00400e3c, NV04_PGRAPH_PASSTHRU_0, NV04_PGRAPH_PASSTHRU_1, NV04_PGRAPH_PASSTHRU_2, NV10_PGRAPH_DIMX_TEXTURE, NV10_PGRAPH_WDIMX_TEXTURE, NV10_PGRAPH_DVD_COLORFMT, NV10_PGRAPH_SCALED_FORMAT, NV04_PGRAPH_MISC24_0, NV04_PGRAPH_MISC24_1, NV04_PGRAPH_MISC24_2, NV03_PGRAPH_X_MISC, NV03_PGRAPH_Y_MISC, NV04_PGRAPH_VALID1, NV04_PGRAPH_VALID2, }; static int nv17_graph_ctx_regs [] = { NV10_PGRAPH_DEBUG_4, 0x004006b0, 0x00400eac, 0x00400eb0, 0x00400eb4, 0x00400eb8, 0x00400ebc, 0x00400ec0, 0x00400ec4, 0x00400ec8, 0x00400ecc, 0x00400ed0, 0x00400ed4, 0x00400ed8, 0x00400edc, 0x00400ee0, 0x00400a00, 0x00400a04, }; void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; int channel, channel_old, i, j; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif // save PGRAPH context for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } nouveau_wait_for_idle(dev); NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context //XXX not working yet #if 1 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]); } nouveau_wait_for_idle(dev); #endif NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACHES, 0x00000001); #endif NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv10_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv10_graph_context_create %d\n", channel); memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ if (dev_priv->chipset>=0x17) { dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); } //XXX should be saved/restored for each fifo //we supposed here we have X fifo and only one 3D fifo. nv10_praph_pipe(dev); return 0; } int nv10_graph_init(drm_device_t *dev) { return 0; }