summaryrefslogtreecommitdiff
path: root/linux-core/i915_buffer.c
AgeCommit message (Collapse)Author
2008-04-06[I915] Fix VRAM eviction.Thomas Hellstrom
2008-01-17i915: fix invalid opcode exception on cpus without clflushKyle McMartin
i915_flush_ttm was unconditionally executing a clflush instruction to (obviously) flush the cache. Instead, check if the cpu supports clflush, and if not, fall back to calling wbinvd to flush the entire cache. Signed-off-by: Kyle McMartin <kmcmartin@redhat.com>
2007-12-21Rename inappropriately named 'mask' fields to 'proposed_flags' instead.Keith Packard
Flags pending validation were stored in a misleadingly named field, 'mask'. As 'mask' is already used to indicate pieces of a flags field which are changing, it seems better to use a name reflecting the actual purpose of this field. I chose 'proposed_flags' as they may not actually end up in 'flags', and in an case will be modified when they are moved over. This affects the API, but not ABI of the user-mode interface.
2007-11-29drm: more cleanupsDave Airlie
2007-11-06i915: cleanup most of the whitespaceDave Airlie
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
Kernel "cleanfile" script run.
2007-10-30drm/i915: add driver cache flush entry pointDave Airlie
Use clflush on Intel hardware to flush cached objects.
2007-10-21Disable i915 accelerated blit copy moves for now until we canThomas Hellstrom
guarantee that it doesn't clash with the X server.
2007-10-12i915: check mask instead of flags for buffer fence typesDave Airlie
2007-09-22Add fence error member.Thomas Hellstrom
Modify the TTM backend bind arguments. Export a number of functions needed for driver-specific super-ioctls. Add a function to map buffer objects from the kernel, regardless of where they're currently placed. A number of error fixes.
2007-07-16drm: detypedef ttm/bo/fence codeDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-06-12Try to make buffer object / fence object ioctl args 64-bit safe.Thomas Hellstrom
Introduce tile members for future tiled buffer support. Allow user-space to explicitly define a fence-class. Remove the implicit fence-class mechanism. 64-bit wide buffer object flag member.
2007-04-18Simplify the ttm backend interface and the agp ttm backend.Thomas Hellstrom
2007-02-16Simple fence object sample driver for via, based on idling the GPU.Thomas Hellstrom
Buffer object driver for via. Some changes to buffer object driver callbacks. Improve fence flushing.
2007-02-15Initial support for fence object classes.Thomas Hellstrom
(Fence objects belonging to different command submission mechanisms).
2007-02-14Set the drm bus map type for each buffer object memory type.Thomas Hellstrom
2007-02-13More bugfixes.Thomas Hellstrom
Fixed memory, pinned buffers and unmappable memory now seems fully functional.
2007-02-12Lindent.Thomas Hellstrom
2007-02-12Cleanup and fix support for pinned buffers.Thomas Hellstrom
2007-02-10Various bugfixes.Thomas Hellstrom
2007-02-09I915 accelerated blit copy functional.Thomas Hellstrom
Fixed - to System memory copies are implemented by flipping in a cache-coherent TTM, blitting to it, and then flipping it out.
2007-02-08Add an accelerated buffer copy cleanup helper.Thomas Hellstrom
Export helper functions and make some important buffer-object functions non-static. Add an i915 accelerated blit buffer move for pci memory buffers.
2007-02-07Checkpoint commit.Thomas Hellstrom
Flag handling and memory type selection cleanup. glxgears won't start.
2007-02-06Simplify pci map vs no pci map choice.Thomas Hellstrom
2007-02-06Implement a policy for selecting memory types.Thomas Hellstrom
2007-02-05i915: Add copy-blit operation.Thomas Hellstrom
2007-02-02Make vm handle buffer objects instead of ttm objects.Thomas Hellstrom
Remove ttm objects. Make vm aware of PCI memory type buffer objects. (Only works for pre 2.6.16 kernels for now).
2007-01-31memory manager: Make device driver aware of different memory types.Thomas Hellstrom
Memory types are either fixed (on-card or pre-bound AGP) or not fixed (dynamically bound) to an aperture. They also carry information about: 1) Whether they can be mapped cached. 2) Whether they are at all mappable. 3) Whether they need an ioremap to be accessible from kernel space. In this way VRAM memory and, for example, pre-bound AGP appear identical to the memory manager. This also makes support for unmappable VRAM simple to implement.
2006-10-18Avoid driver-specific AGP user-populated types, since we don't know what AGPThomas Hellstrom
driver we're on. Avoid global cache flushes before inserting pages. In general, they are never mapped, and not accessed through the kernel map, so a cache flush should not be necessary. The exception is pages that are bound cached. We might need a cache flush for those.
2006-10-17Lindent.Thomas Hellstrom
2006-10-16Change Intel AGP memory type numbers.Thomas Hellstrom
2006-10-12Simplify the AGP backend interface somewhat.Thomas Hellstrom
Fix buffer bound caching policy changing, Allow on-the-fly changing of caching policy on bound buffers if the hardware supports it. Allow drivers to use driver-specific AGP memory types for TTM AGP pages. Will make AGP drivers much easier to migrate.
2006-09-26Allow for a driver to overload the ttm backend object methods.Thomas Hellstrom
2006-09-12Use lazy fence wait when possible even for RW fences. Saves some CPU.Thomas Hellstrom
Lindent.
2006-09-01Various bugfixes.Thomas Hellstrom
2006-08-31Validation and fencing.Thomas Hellstrom
2006-08-22Initial i915 buffer object driverThomas Hellstrom
handle; int depth_offset; int depth_size; drm_handle_t tex_handle; int tex_offset; int tex_size; int log_tex_granularity; int pitch; int rotation; /* 0, 90, 180 or 270 */ int rotated_offset; int rotated_size; int rotated_pitch; int virtualX, virtualY; unsigned int front_tiled; unsigned int back_tiled; unsigned int depth_tiled; unsigned int rotated_tiled; unsigned int rotated2_tiled; int pipeA_x; int pipeA_y; int pipeA_w; int pipeA_h; int pipeB_x; int pipeB_y; int pipeB_w; int pipeB_h; /* Triple buffering */ drm_handle_t third_handle; int third_offset; int third_size; unsigned int third_tiled; } drm_i915_sarea_t; /* Driver specific fence types and classes. */ /* The only fence class we support */ #define DRM_I915_FENCE_CLASS_ACCEL 0 /* Fence type that guarantees read-write flush */ #define DRM_I915_FENCE_TYPE_RW 2 /* MI_FLUSH programmed just before the fence */ #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 /* Flags for perf_boxes */ #define I915_BOX_RING_EMPTY 0x1 #define I915_BOX_FLIP 0x2 #define I915_BOX_WAIT 0x4 #define I915_BOX_TEXTURE_LOAD 0x8 #define I915_BOX_LOST_CONTEXT 0x10 /* I915 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_I915_INIT 0x00 #define DRM_I915_FLUSH 0x01 #define DRM_I915_FLIP 0x02 #define DRM_I915_BATCHBUFFER 0x03 #define DRM_I915_IRQ_EMIT 0x04 #define DRM_I915_IRQ_WAIT 0x05 #define DRM_I915_GETPARAM 0x06 #define DRM_I915_SETPARAM 0x07 #define DRM_I915_ALLOC 0x08 #define DRM_I915_FREE 0x09 #define DRM_I915_INIT_HEAP 0x0a #define DRM_I915_CMDBUFFER 0x0b #define DRM_I915_DESTROY_HEAP 0x0c #define DRM_I915_SET_VBLANK_PIPE 0x0d #define DRM_I915_GET_VBLANK_PIPE 0x0e #define DRM_I915_VBLANK_SWAP 0x0f #define DRM_I915_MMIO 0x10 #define DRM_I915_HWS_ADDR 0x11 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) /* Asynchronous page flipping: */ typedef struct drm_i915_flip { int pipes; } drm_i915_flip_t; /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. */ typedef struct _drm_i915_batchbuffer { int start; /* agp offset */ int used; /* nr bytes in use */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer_t; /* As above, but pass a pointer to userspace buffer which can be * validated by the kernel prior to sending to hardware. */ typedef struct _drm_i915_cmdbuffer { char __user *buf; /* pointer to userspace command buffer */ int sz; /* nr bytes in buf */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer_t; /* Userspace can request & wait on irq's: */ typedef struct drm_i915_irq_emit { int __user *irq_seq; } drm_i915_irq_emit_t; typedef struct drm_i915_irq_wait { int irq_seq; } drm_i915_irq_wait_t; /* Ioctl to query kernel params: */ #define I915_PARAM_IRQ_ACTIVE 1 #define I915_PARAM_ALLOW_BATCHBUFFER 2 #define I915_PARAM_LAST_DISPATCH 3 typedef struct drm_i915_getparam { int param; int __user *value; } drm_i915_getparam_t; /* Ioctl to set kernel params: */ #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 typedef struct drm_i915_setparam { int param; int value; } drm_i915_setparam_t; /* A memory manager for regions of shared memory: */ #define I915_MEM_REGION_AGP 1 typedef struct drm_i915_mem_alloc { int region; int alignment; int size; int __user *region_offset; /* offset from start of fb or agp */ } drm_i915_mem_alloc_t; typedef struct drm_i915_mem_free { int region; int region_offset; } drm_i915_mem_free_t; typedef struct drm_i915_mem_init_heap { int region; int size; int start; } drm_i915_mem_init_heap_t; /* Allow memory manager to be torn down and re-initialized (eg on * rotate): */ typedef struct drm_i915_mem_destroy_heap { int region; } drm_i915_mem_destroy_heap_t; /* Allow X server to configure which pipes to monitor for vblank signals */ #define DRM_I915_VBLANK_PIPE_A 1 #define DRM_I915_VBLANK_PIPE_B 2 typedef struct drm_i915_vblank_pipe { int pipe; } drm_i915_vblank_pipe_t; /* Schedule buffer swap at given vertical blank: */ typedef struct drm_i915_vblank_swap { drm_drawable_t drawable; enum drm_vblank_seq_type seqtype; unsigned int sequence; } drm_i915_vblank_swap_t; #define I915_MMIO_READ 0 #define I915_MMIO_WRITE 1 #define I915_MMIO_MAY_READ 0x1 #define I915_MMIO_MAY_WRITE 0x2 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0 #define MMIO_REGS_IA_VERTICES_COUNT 1 #define MMIO_REGS_VS_INVOCATION_COUNT 2 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3 #define MMIO_REGS_GS_INVOCATION_COUNT 4 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5 #define MMIO_REGS_CL_INVOCATION_COUNT 6 #define MMIO_REGS_PS_INVOCATION_COUNT 7 #define MMIO_REGS_PS_DEPTH_COUNT 8 typedef struct drm_i915_mmio_entry { unsigned int flag; unsigned int offset; unsigned int size; }drm_i915_mmio_entry_t; typedef struct drm_i915_mmio { unsigned int read_write:1; unsigned int reg:31; void __user *data; } drm_i915_mmio_t; typedef struct drm_i915_hws_addr { uint64_t addr; } drm_i915_hws_addr_t; #endif /* _I915_DRM_H_ */