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path: root/linux-core/drm_stub.c
AgeCommit message (Expand)Author
2007-03-23cleanup more whitespace from ttm mergeDave Airlie
2007-02-14Merge branch 'ttm-vram-0-1-branch'Thomas Hellstrom
2007-02-13Bugzilla Bug #9457Thomas Hellstrom
2007-02-06Implement a policy for selecting memory types.Thomas Hellstrom
2007-01-01fixup permission along line of kernelDave Airlie
2006-12-19drm: remove all 2.4 support for drm development tree.Dave Airlie
2006-12-15Remove the memory caches for fence objects and memory manager nodes,Thomas Hellstrom
2006-10-18Merging drm-ttm-0-2-branchThomas Hellstrom
2006-10-17Add vma list memory usage to memory accounting.Thomas Hellstrom
2006-10-17Extend generality for more memory types.Thomas Hellstrom
2006-10-10Use a nopage-based approach to fault in pfns.Thomas Hellstrom
2006-10-02Add a buffer object manager for TTM maps.Thomas Hellstrom
2006-10-02Make locked tasklet handling more robust.Michel Dänzer
2006-09-29Add support for tracking drawable information to coreMichel Dänzer
2006-09-28Add support for tracking drawable information to coreMichel Dänzer
2006-09-06Put the PCI device/vendor id in the drm_device_t.Eric Anholt
2006-09-04Make memory caches global so that they can be used withThomas Hellstrom
2006-09-01Bugfixes,Thomas Hellstrom
2006-08-28Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into drm-...Thomas Hellstrom
2006-08-28drm: lots of small cleanups and whitespace issues fixed upDave Airlie
2006-08-28remove local copies of pci domain/bus/slot/numDave Airlie
2006-08-21User / Kernel space fence objects (device-independent part).Thomas Hellstrom
2006-08-21Generic DRM support base-class support for user-space objects, likeThomas Hellstrom
2006-07-24switch drm to use Linux mutexes instead of semaphore.Dave Airlie
2006-07-10Change drm Map handles to be arbitrary 32-bit hash tokens in the rangeThomas Hellstrom
2006-02-18always enable and set master on pci deviceDave Airlie
2006-02-18major realigment of DRM CVS with kernel code, makes integration much easierDave Airlie
2006-01-02use drm_cards_limit instead of cards_limitDave Airlie
2005-08-05Rename the driver hooks in the DRM to something a little moreEric Anholt
2005-07-03Simplify the sysfs codeJon Smirl
2005-07-03Add sysfs attribute dri_library_name on Linux. code in share-core/via_drv.cJon Smirl
2005-06-28Given that BenH says using the sysdev approach for DRM is bogus, I'll yankAlan Hourihane
2005-06-23Fix drm_memory_debug.c to compile, doesn't seem to be working Clean upJon Smirl
2005-06-22Get the power management hooks into the right place so that everything getsJon Smirl
2005-06-04misc cleanup patch from Adrian BunkDave Airlie
2005-05-28Actually check for drm_fb_loaded before trying to initialize the sysdevAlan Hourihane
2005-05-28Re-implement the power management.Alan Hourihane
2005-05-16Added device_is_agp callback to drm_driver. This function is called by theIan Romanick
2005-03-25fix up AGP multi-head support for kernel 2.6.12Dave Airlie
2005-03-25For 2.6.12 and 2.6.11.x:Dave Airlie
2005-02-07change DRIVER_ to CORE_ makes things look nicer, also change it so theDave Airlie
2004-10-29Switch SPIN_LOCK_UNLOCKED to spin_lock_init()Jon Smirl
2004-10-29Add include of moduleparam.hJon Smirl
2004-10-23Prepare to eliminate inter_module_get("agp")Jon Smirl
2004-10-20Switch linux-core from using dev->pdev->driver->name toJon Smirl
2004-10-18Update Doxygen configuration & comments.Jose Fonseca
2004-10-15Switch linux-core over to 2.6 parameter model to enable debug useJon Smirl
2004-10-12Breakout heads into their own data structures.Jon Smirl
2004-10-10Rename fn_tbl to driver. Core driver now uses pci_driver name whichJon Smirl
2004-10-05enable the device in the right order, remove __devinit from drm_intJon Smirl
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-09 08:56:18 +0000
rm.h" #include "nouveau_drv.h" struct nv50_fifo_priv { struct nouveau_gpuobj_ref *thingo[2]; int cur_thingo; }; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) static void nv50_fifo_init_thingo(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; struct nouveau_gpuobj_ref *cur; int i, nr; DRM_DEBUG("\n"); cur = priv->thingo[priv->cur_thingo]; priv->cur_thingo = !priv->cur_thingo; /* We never schedule channel 0 or 127 */ for (i = 1, nr = 0; i < 127; i++) { if (dev_priv->fifos[i]) { INSTANCE_WR(cur->gpuobj, nr++, i); } } NV_WRITE(0x32f4, cur->instance >> 12); NV_WRITE(0x32ec, nr); NV_WRITE(0x2500, 0x101); } static int nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; uint32_t inst; DRM_DEBUG("ch%d\n", channel); if (!chan->ramfc) return -EINVAL; if (IS_G80) inst = chan->ramfc->instance >> 12; else inst = chan->ramfc->instance >> 8; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); if (!nt) nv50_fifo_init_thingo(dev); return 0; } static void nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t inst; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80; else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst); if (!nt) nv50_fifo_init_thingo(dev); } static void nv50_fifo_init_reset(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pmc_e = NV_PMC_ENABLE_PFIFO; DRM_DEBUG("\n"); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e); } static void nv50_fifo_init_intr(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); } static void nv50_fifo_init_context_table(struct drm_device *dev) { int i; DRM_DEBUG("\n"); for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) nv50_fifo_channel_disable(dev, i, 1); nv50_fifo_init_thingo(dev); } static void nv50_fifo_init_regs__nv(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(0x250c, 0x6f3cfc34); } static void nv50_fifo_init_regs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(0x2500, 0); NV_WRITE(0x3250, 0); NV_WRITE(0x3220, 0); NV_WRITE(0x3204, 0); NV_WRITE(0x3210, 0); NV_WRITE(0x3270, 0); /* Enable dummy channels setup by nv50_instmem.c */ nv50_fifo_channel_enable(dev, 0, 1); nv50_fifo_channel_enable(dev, 127, 1); } int nv50_fifo_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv50_fifo_priv *priv; int ret; DRM_DEBUG("\n"); priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) return -ENOMEM; dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); nv50_fifo_init_intr(dev); ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]); if (ret) { DRM_ERROR("error creating thingo0: %d\n", ret); return ret; } ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]); if (ret) { DRM_ERROR("error creating thingo1: %d\n", ret); return ret; } nv50_fifo_init_context_table(dev); nv50_fifo_init_regs__nv(dev); nv50_fifo_init_regs(dev); return 0; } void nv50_fifo_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; DRM_DEBUG("\n"); if (!priv) return; nouveau_gpuobj_ref_del(dev, &priv->thingo[0]); nouveau_gpuobj_ref_del(dev, &priv->thingo[1]); dev_priv->Engine.fifo.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } int nv50_fifo_channel_id(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) & NV50_PFIFO_CACHE1_PUSH1_CHID_MASK); } int nv50_fifo_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramfc = NULL; int ret; DRM_DEBUG("ch%d\n", chan->id); if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start; ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc); if (ret) return ret; } else { ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &chan->ramfc); if (ret) return ret; ramfc = chan->ramfc->gpuobj; } INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4); INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4)); INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */ INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff); INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff); INSTANCE_WR(ramfc, 0x10/4, 0x00000000); INSTANCE_WR(ramfc, 0x08/4, 0x00000000); INSTANCE_WR(ramfc, 0x40/4, 0x00000000); INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0); INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); INSTANCE_WR(ramfc, 0x78/4, 0x00000000); INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); if (!IS_G80) { INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id); INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } ret = nv50_fifo_channel_enable(dev, chan->id, 0); if (ret) { DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; } return 0; } void nv50_fifo_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("ch%d\n", chan->id); nv50_fifo_channel_disable(dev, chan->id, 0); /* Dummy channel, also used on ch 127 */ if (chan->id == 0) nv50_fifo_channel_disable(dev, 127, 0); if ((NV_READ(NV03_PFIFO_CACHE1_PUSH1) & 0xffff) == chan->id) NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 127); nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv50_fifo_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; DRM_DEBUG("ch%d\n", chan->id); /*XXX: incomplete, only touches the regs that NV does */ NV_WRITE(0x3244, 0); NV_WRITE(0x3240, 0); NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4)); NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4)); NV_WRITE(0x3254, 1); NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4)); if (!IS_G80) { NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4)); NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); } NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); return 0; } int nv50_fifo_save_context(struct nouveau_channel *chan) { DRM_DEBUG("ch%d\n", chan->id); DRM_ERROR("stub!\n"); return 0; }
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-09 08:56:16 +0000