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path: root/bsd-core/drm_sysctl.c
AgeCommit message (Collapse)Author
2005-08-05Rename the driver hooks in the DRM to something a little moreEric Anholt
understandable: preinit -> load postinit -> (removed) presetup -> firstopen postsetup -> (removed) open_helper -> open prerelease -> preclose free_filp_priv -> postclose pretakedown -> lastclose postcleanup -> unload release -> reclaim_buffers_locked version -> (removed) postinit and version were replaced with generic code in the Linux DRM (drivers now set their version numbers and description in the driver structure, like on BSD). postsetup wasn't used at all. Fixes the savage hooks for initializing and tearing down mappings at the right times. Testing involved at least starting X, running glxgears, killing glxgears, exiting X, and repeating. Tested on: FreeBSD (g200, g400, r200, r128) Linux (r200, savage4)
2005-04-16Use /*- to begin license blocks in BSD code to reduce diffs against FreeBSDEric Anholt
CVS.
2005-02-13Fix bad copy'n'pastage of copyrights -- don't disclaim anything for VAEric Anholt
Linux or PI in my copyrights when I should be doing it for myself.
2005-02-05- Implement drm_initmap, and extend it with the resource number to helpEric Anholt
FreeBSD. Add drm_get_resource_{start|len} so linux-specific stuff doesn't need to be in shared code. - Fix mach64 build by using __DECONST to work around passing a const pointer to useracc, which is unfortunately not marked const. - Get rid of a lot of maplist code by not having dev->maplist be a pointer, and by sticking the link entries directly in drm_local_map_t rather than having a separate structure for the linked list. - Factor out map uninit and removal into its own routine, rather than duplicating in both drm_takedown() and drm_rmmap(). - Hook up more driver functions, and correct FreeBSD-specific bits of radeon_cp.c, making radeon work. - Baby steps towards using bus_space as we should.
2004-12-15Use SYSCTL_ADD_OID macro instead of calling function directly.Eric Anholt
Submitted by: reffie@FreeBSD.org
2004-11-07Now that the memory debug code is gone, and all 3 BSDs have M_ZERO, stopEric Anholt
using drm_alloc/drm_free in the core and instead use plain malloc/free.
2004-11-06Hook the debug output up to a sysctl, so you can choose to enable atEric Anholt
runtime.
2004-11-06Commit first pieces of port to OpenBSD, done by Martin Lexa (martin atEric Anholt
martinlexa dot cz). Now that we've got porting for all three major BSDs (and the fourth being very similar to FreeBSD), move the mostly-duplication drm_os_* files into drmP.h. Remove some cruft from linux heritage and from pieces of the DRM that have since been removed. Note that things are still not quite working for even FreeBSD, but these are first steps at cleanup, and just a WIP checkpoint.
2004-11-06Remove the vestiges of the memory-debug code.Eric Anholt
2004-11-06Commit WIP of BSD conversion to core model. Compiles for r128, radeon, butEric Anholt
doesn't run yet. Moves the ioctl definitions for these two drivers back to the shared code -- they aren't OS-specific.
2003-12-16Don't ioremap the framebuffer area. The ioremapped area wasn't used byEric Anholt
anything, and took up valuable KVA. While I'm in the area, clean up BSD MTRR stuff some more. Suggested by: jonsmirl
2003-10-24Don't try to use dev->dma_lock unless dma is initialized (dev->dma != NULL)Eric Anholt
in bufs_info sysctl handler. dev->dma and dev->dma_lock existence are protected by DRM_LOCK(). Fixes panic on sysctl hw.dri when the device is uninitialied (when you aren't in X).
2003-10-22Fix warning about static DRM(bufs_info) defined but not used in theEric Anholt
!__HAVE_DMA case.
2003-10-20Fix the possibility of sleeping with locks held in sysctls by copying theEric Anholt
data into temporary variables with the lock held then outputting to sysctls with the lock released. Rearranged a little extra code to aid this. Note that drm_memory_debug.h hasn't had this fix applied, but I consider that code to be just about dead anyway.
2003-10-19- SMPng lock the DRM. This is only partial -- there are a few code pathsEric Anholt
used by root (the X Server) which are not locked. However, it should deal with lost-IRQ issues on -current which I think people have been experiencing but I am unable to reproduce (though I understand why they would occur, because of a bug of mine). Note that most of the locking (DRM_LOCK()/UNLOCK()) is all covered by Giant still, so it doesn't matter yet. - Remove locking on FreeBSD-stable and NetBSD. These are covered by the fact that there is no reentrancy of the kernel except by interrupts, which are locked using spldrm()/splx() instead.
2003-10-03Stylistic preparation for SMPng locking work: DRM_LOCK/DRM_UNLOCK have sideEric Anholt
effects, so make them look like functions (add parenthesis).
2003-10-02Add an MIT-style copyright, assigned to myself, to these files. I thinkEric Anholt
I've touched enough of the code here, and there was no previous copyright. Do some drive-by style fixes while I'm here.
2003-08-19- Remove $FreeBSD$ tags as they weren't too useful and merges are now beingEric Anholt
done through perforce. - Add copyright headers to drm_os_*bsd.h, still need to research the other copyright-less files better.
2003-04-26Fix formatting of hw.dri sysctl.Eric Anholt
2003-04-26Missed files in the last commit: Remove memory debugging sysctl unlessEric Anholt
MEMORY_DEBUG is set.
2003-04-25Merge from FreeBSD-current.Eric Anholt
2003-04-24Remove more gamma DMA infrastructure. Most of this code was copied straightEric Anholt
from linux, so it could be added back if some driver needed it in the future.
2003-04-24Remove DRM_DMA_HISTOGRAM and associated code.Eric Anholt
2003-03-29Remove dead vma code and remove the unused devstate struct definition.Eric Anholt
2003-03-11Merge back from FreeBSD-current, adding FreeBSD ID tags to aid futureEric Anholt
merging. Also includes an update to radeon PCI IDs.
2003-02-21Merge from bsd-4-0-0-branch.Eric Anholt
2002-09-29warnings cleanupEric Anholt
2002-07-05merged bsd-3-0-0-branchAlan Hourihane
2002-01-27Import of XFree86 4.2.0David Dawes
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/*
 * Copyright 2005-2006 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"


/* returns the size of fifo context */
int nouveau_fifo_ctx_size(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv=dev->dev_private;

	if (dev_priv->card_type >= NV_40)
		return 128;
	else if (dev_priv->card_type >= NV_17)
		return 64;
	else
		return 32;
}

/***********************************
 * functions doing the actual work
 ***********************************/

static int nouveau_fifo_instmem_configure(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	NV_WRITE(NV03_PFIFO_RAMHT,
			(0x03 << 24) /* search 128 */ |
			((dev_priv->ramht_bits - 9) << 16) |
			(dev_priv->ramht_offset >> 8)
			);

	NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);

	switch(dev_priv->card_type)
	{
		case NV_40:
			switch (dev_priv->chipset) {
			case 0x47:
			case 0x49:
			case 0x4b:
				NV_WRITE(0x2230, 1);
				break;
			default:
				break;
			}
			NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
			break;
		case NV_44:
			NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
					(2 << 16));
			break;
		case NV_30:
		case NV_20:
		case NV_17:
			NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
					(1 << 16) /* 64 Bytes entry*/);
			/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
			break;
		case NV_11:
		case NV_10:
		case NV_04:
			NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
			break;
	}

	return 0;
}

int nouveau_fifo_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PFIFO);
	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PFIFO);

	/* Enable PFIFO error reporting */
	NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
	NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);

	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);

	ret = nouveau_fifo_instmem_configure(dev);
	if (ret) {
		DRM_ERROR("Failed to configure instance memory\n");
		return ret;
	}

	/* FIXME remove all the stuff that's done in nouveau_fifo_alloc */

	DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");

	/* All channels into PIO mode */
	NV_WRITE(NV04_PFIFO_MODE, 0x00000000);

	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
	/* Channel 0 active, PIO mode */
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
	/* PUT and GET to 0 */
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
	/* No cmdbuf object */
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
	NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
	NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
	NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
	NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
	NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);

	NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
				      NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
				      NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
				      NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
				      0x00000000);

	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);

	/* FIXME on NV04 */
	if (dev_priv->card_type >= NV_10) {
		NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
		NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
		if (dev_priv->card_type >= NV_40)
			NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
		else
			NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
	} else {
		NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
		NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
		NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
	}

	NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
	return 0;
}

static int
nouveau_fifo_pushbuf_ctxdma_init(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct mem_block *pb = chan->pushbuf_mem;
	struct nouveau_gpuobj *pushbuf = NULL;
	int ret;

	if (pb->flags & NOUVEAU_MEM_AGP) {
		ret = nouveau_gpuobj_gart_dma_new(chan, pb->start, pb->size,
						  NV_DMA_ACCESS_RO,
						  &pushbuf,
						  &chan->pushbuf_base);
	} else
	if (pb->flags & NOUVEAU_MEM_PCI) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     pb->start, pb->size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_PCI_NONLINEAR,
					     &pushbuf);
		chan->pushbuf_base = 0;
	} else if (dev_priv->card_type != NV_04) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     pb->start, pb->size,
					     NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_VIDMEM, &pushbuf);
		chan->pushbuf_base = 0;
	} else {
		/* NV04 cmdbuf hack, from original ddx.. not sure of it's
		 * exact reason for existing :)  PCI access to cmdbuf in
		 * VRAM.
		 */
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     pb->start +
					       drm_get_resource_start(dev, 1),
					     pb->size, NV_DMA_ACCESS_RO,
					     NV_DMA_TARGET_PCI, &pushbuf);
		chan->pushbuf_base = 0;
	}

	if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf,
					  &chan->pushbuf))) {
		DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret);
		if (pushbuf != dev_priv->gart_info.sg_ctxdma)
			nouveau_gpuobj_del(dev, &pushbuf);
		return ret;
	}

	return 0;
}

static struct mem_block *
nouveau_fifo_user_pushbuf_alloc(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_config *config = &dev_priv->config;
	struct mem_block *pb;
	int pb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);

	/* Defaults for unconfigured values */
	if (!config->cmdbuf.location)
		config->cmdbuf.location = NOUVEAU_MEM_FB;
	if (!config->cmdbuf.size || config->cmdbuf.size < pb_min_size)
		config->cmdbuf.size = pb_min_size;

	pb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
			       config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
			       (struct drm_file *)-2);
	if (!pb)
		DRM_ERROR("Couldn't allocate DMA push buffer.\n");

	return pb;
}

/* allocates and initializes a fifo for user space consumption */
int
nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
		   struct drm_file *file_priv, struct mem_block *pushbuf,
		   uint32_t vram_handle, uint32_t tt_handle)
{
	int ret;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	struct nouveau_channel *chan;
	int channel;

	/*
	 * Alright, here is the full story
	 * Nvidia cards have multiple hw fifo contexts (praise them for that,
	 * no complicated crash-prone context switches)
	 * We allocate a new context for each app and let it write to it directly
	 * (woo, full userspace command submission !)
	 * When there are no more contexts, you lost
	 */
	for (channel = 0; channel < engine->fifo.channels; channel++) {
		if (dev_priv->fifos[channel] == NULL)
			break;
	}

	/* no more fifos. you lost. */
	if (channel == engine->fifo.channels)
		return -EINVAL;

	dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
					      DRM_MEM_DRIVER);
	if (!dev_priv->fifos[channel])
		return -ENOMEM;
	dev_priv->fifo_alloc_count++;
	chan = dev_priv->fifos[channel];
	chan->dev = dev;
	chan->id = channel;
	chan->file_priv = file_priv;
	chan->pushbuf_mem = pushbuf;

	DRM_INFO("Allocating FIFO number %d\n", channel);

	/* Locate channel's user control regs */
	if (dev_priv->card_type < NV_40) {
		chan->user = NV03_USER(channel);
		chan->user_size = NV03_USER_SIZE;
		chan->put = NV03_USER_DMA_PUT(channel);
		chan->get = NV03_USER_DMA_GET(channel);
		chan->ref_cnt = NV03_USER_REF_CNT(channel);
	} else
	if (dev_priv->card_type < NV_50) {
		chan->user = NV40_USER(channel);
		chan->user_size = NV40_USER_SIZE;
		chan->put = NV40_USER_DMA_PUT(channel);
		chan->get = NV40_USER_DMA_GET(channel);
		chan->ref_cnt = NV40_USER_REF_CNT(channel);
	} else {
		chan->user = NV50_USER(channel);
		chan->user_size = NV50_USER_SIZE;
		chan->put = NV50_USER_DMA_PUT(channel);
		chan->get = NV50_USER_DMA_GET(channel);
		chan->ref_cnt = NV50_USER_REF_CNT(channel);
	}

	/* Allocate space for per-channel fixed notifier memory */
	ret = nouveau_notifier_init_channel(chan);
	if (ret) {
		nouveau_fifo_free(chan);
		return ret;
	}

	/* Setup channel's default objects */
	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
	if (ret) {
		nouveau_fifo_free(chan);
		return ret;
	}

	/* Create a dma object for the push buffer */
	ret = nouveau_fifo_pushbuf_ctxdma_init(chan);
	if (ret) {
		nouveau_fifo_free(chan);
		return ret;
	}

	nouveau_wait_for_idle(dev);

	/* disable the fifo caches */
	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);

	/* Create a graphics context for new channel */
	ret = engine->graph.create_context(chan);
	if (ret) {
		nouveau_fifo_free(chan);
		return ret;
	}

	/* Construct inital RAMFC for new channel */
	ret = engine->fifo.create_context(chan);
	if (ret) {
		nouveau_fifo_free(chan);
		return ret;
	}

	/* setup channel's default get/put values
	 * XXX: quite possibly extremely pointless..
	 */
	NV_WRITE(chan->get, chan->pushbuf_base);
	NV_WRITE(chan->put, chan->pushbuf_base);

	/* If this is the first channel, setup PFIFO ourselves.  For any
	 * other case, the GPU will handle this when it switches contexts.
	 */
	if (dev_priv->fifo_alloc_count == 1) {
		ret = engine->fifo.load_context(chan);
		if (ret) {
			nouveau_fifo_free(chan);
			return ret;
		}

		ret = engine->graph.load_context(chan);
		if (ret) {
			nouveau_fifo_free(chan);
			return ret;
		}
	}

	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);

	/* reenable the fifo caches */
	NV_WRITE(NV03_PFIFO_CACHES, 1);

	DRM_INFO("%s: initialised FIFO %d\n", __func__, channel);
	*chan_ret = chan;
	return 0;
}

static int
nouveau_channel_idle(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	uint32_t caches;
	int idle;

	caches = NV_READ(NV03_PFIFO_CACHES);
	NV_WRITE(NV03_PFIFO_CACHES, caches & ~1);

	if (engine->fifo.channel_id(dev) != chan->id) {
		struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;

		if (INSTANCE_RD(ramfc, 0) != INSTANCE_RD(ramfc, 1))
			idle = 0;
		else
			idle = 1;
	} else {
		idle = (NV_READ(NV04_PFIFO_CACHE1_DMA_GET) ==
			NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
	}

	NV_WRITE(NV03_PFIFO_CACHES, caches);
	return idle;
}

/* stops a fifo */
void nouveau_fifo_free(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	uint64_t t_start;

	DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id);

	/* Give the channel a chance to idle, wait 2s (hopefully) */
	t_start = engine->timer.read(dev);
	while (!nouveau_channel_idle(chan)) {
		if (engine->timer.read(dev) - t_start > 2000000000ULL) {
			DRM_ERROR("Failed to idle channel %d before destroy."
				  "Prepare for strangeness..\n", chan->id);
			break;
		}
	}

	/*XXX: Maybe should wait for PGRAPH to finish with the stuff it fetched
	 *     from CACHE1 too?
	 */

	/* disable the fifo caches */
	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);

	// FIXME XXX needs more code

	engine->fifo.destroy_context(chan);

	/* Cleanup PGRAPH state */
	engine->graph.destroy_context(chan);

	/* reenable the fifo caches */
	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);

	/* Deallocate push buffer */
	nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
	if (chan->pushbuf_mem) {
		nouveau_mem_free(dev, chan->pushbuf_mem);
		chan->pushbuf_mem = NULL;
	}

	/* Destroy objects belonging to the channel */
	nouveau_gpuobj_channel_takedown(chan);

	nouveau_notifier_takedown_channel(chan);

	dev_priv->fifos[chan->id] = NULL;
	dev_priv->fifo_alloc_count--;
	drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
}

/* cleanups all the fifos from file_priv */
void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	int i;

	DRM_DEBUG("clearing FIFO enables from file_priv\n");
	for(i = 0; i < engine->fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->file_priv == file_priv)
			nouveau_fifo_free(chan);
	}
}

int
nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv,
		   int channel)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	if (channel >= engine->fifo.channels)
		return 0;
	if (dev_priv->fifos[channel] == NULL)
		return 0;
	return (dev_priv->fifos[channel]->file_priv == file_priv);
}

/***********************************
 * ioctls wrapping the functions
 ***********************************/

static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
				    struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_nouveau_channel_alloc *init = data;
	struct drm_map_list *entry;
	struct nouveau_channel *chan;
	struct mem_block *pushbuf;
	int res;

	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;

	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
		return -EINVAL;

	pushbuf = nouveau_fifo_user_pushbuf_alloc(dev);
	if (!pushbuf)
		return -ENOMEM;

	res = nouveau_fifo_alloc(dev, &chan, file_priv, pushbuf,
				 init->fb_ctxdma_handle,
				 init->tt_ctxdma_handle);
	if (res)
		return res;
	init->channel  = chan->id;
	init->put_base = chan->pushbuf_base;

	/* make the fifo available to user space */
	/* first, the fifo control regs */
	init->ctrl = dev_priv->mmio->offset + chan->user;
	init->ctrl_size = chan->user_size;
	res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
			 0, &chan->regs);
	if (res != 0)
		return res;

	entry = drm_find_matching_map(dev, chan->regs);
	if (!entry)
		return -EINVAL;
	init->ctrl = entry->user_token;

	/* pass back FIFO map info to the caller */
	init->cmdbuf      = chan->pushbuf_mem->map_handle;
	init->cmdbuf_size = chan->pushbuf_mem->size;

	/* and the notifier block */
	init->notifier      = chan->notifier_block->map_handle;
	init->notifier_size = chan->notifier_block->size;

	return 0;
}

static int nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
				   struct drm_file *file_priv)
{
	struct drm_nouveau_channel_free *cfree = data;
	struct nouveau_channel *chan;

	NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);

	nouveau_fifo_free(chan);
	return 0;
}

/***********************************
 * finally, the ioctl table
 ***********************************/

struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH),
};

int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-08 01:09:39 +0000