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path: root/bsd-core/drm_fops.c
AgeCommit message (Expand)Author
2007-08-15BSD: Replace brief description in each file's first line with doxygen later on.Eric Anholt
2007-08-13Bug #11951: Fix an errno sign inversion on pre-FreeBSD 5.vehemens
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
2005-08-26[1] Fix BSD DRM for the nonroot changes. [2] Don't attempt to acquire theEric Anholt
2005-08-05Rename the driver hooks in the DRM to something a little moreEric Anholt
2005-04-16Use /*- to begin license blocks in BSD code to reduce diffs against FreeBSDEric Anholt
2005-02-05- Implement drm_initmap, and extend it with the resource number to helpEric Anholt
2004-11-07Now that the memory debug code is gone, and all 3 BSDs have M_ZERO, stopEric Anholt
2004-11-06Commit WIP of BSD conversion to core model. Compiles for r128, radeon, butEric Anholt
2004-08-17Merged drmfntbl-0-0-1Dave Airlie
2004-07-06MFC as of 20040705: dev_t -> struct cdev * change.Eric Anholt
2003-11-12Fix a locking nit, and add asserts in some things that should be calledEric Anholt
2003-11-04Memory layout transition:Michel Daenzer
2003-10-19- SMPng lock the DRM. This is only partial -- there are a few code pathsEric Anholt
2003-10-03Stylistic preparation for SMPng locking work: DRM_LOCK/DRM_UNLOCK have sideEric Anholt
2003-08-19- Remove $FreeBSD$ tags as they weren't too useful and merges are now beingEric Anholt
2003-04-25Merge from FreeBSD-current.Eric Anholt
2003-04-24Move one definition to drm_drv.h and remove the rest of drm_init.h whichEric Anholt
2003-04-24Make DRM(read) and DRM(poll) stubs and remove DRM(write) andEric Anholt
2003-03-11Merge back from FreeBSD-current, adding FreeBSD ID tags to aid futureEric Anholt
2003-02-21Merge from bsd-4-0-0-branch.Eric Anholt
2002-07-05merged bsd-3-0-0-branchAlan Hourihane
2002-01-27Initial revisionDavid Dawes
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 16:23:49 +0000
R ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Thomas Hellstrom. * Register info from Digeo Inc. */ #ifndef _VIA_DMABLIT_H #define _VIA_DMABLIT_H #include <linux/dma-mapping.h> #define VIA_NUM_BLIT_ENGINES 2 #define VIA_NUM_BLIT_SLOTS 8 struct _drm_via_descriptor; typedef struct _drm_via_sg_info { struct page **pages; unsigned long num_pages; struct _drm_via_descriptor **desc_pages; int num_desc_pages; int num_desc; enum dma_data_direction direction; unsigned char *bounce_buffer; dma_addr_t chain_start; uint32_t free_on_sequence; unsigned int descriptors_per_page; int aborted; enum { dr_via_device_mapped, dr_via_desc_pages_alloc, dr_via_pages_locked, dr_via_pages_alloc, dr_via_sg_init } state; } drm_via_sg_info_t; typedef struct _drm_via_blitq { drm_device_t *dev; uint32_t cur_blit_handle; uint32_t done_blit_handle; unsigned serviced; unsigned head; unsigned cur; unsigned num_free; unsigned num_outstanding; unsigned long end; int aborting; int is_active; drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; spinlock_t blit_lock; wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; wait_queue_head_t busy_queue; struct work_struct wq; struct timer_list poll_timer; } drm_via_blitq_t; /* * PCI DMA Registers * Channels 2 & 3 don't seem to be implemented in hardware. */ #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ /* Define for DMA engine */ /* DPR */ #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ /* MR */ #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ /* CSR */ #define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 16:23:49 +0000