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AgeCommit message (Expand)Author
2006-10-17Implement mm_lock and mm_unlock functions.Thomas Hellstrom
2006-10-17Useful output on a FIFO error interrupt.Ben Skeggs
2006-10-17typoBen Skeggs
2006-10-17Remove the memory manager parameter from the put_block function, as thisThomas Hellstrom
2006-10-17Extend generality for more memory types.Thomas Hellstrom
2006-10-16dev->agp_buffer_map is not initialized for AGP DMA on savagesMichael Karcher
2006-10-17NV40: *Now* fifo ctx switching works for me..Ben Skeggs
2006-10-17NV40: FIFO context switching now WorksForMe(tm)Ben Skeggs
2006-10-17Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ...Ben Skeggs
2006-10-17Some info on NV40's RAMFCBen Skeggs
2006-10-16Change Intel AGP memory type numbers.Thomas Hellstrom
2006-10-15Merge branch 'master' of git://anongit.freedesktop.org/git/mesa/drm into nouv...Stephane Marchesin
2006-10-14Again more work on context switches. They work, sometimes. And when they do t...Stephane Marchesin
2006-10-14remove config.h from build no longer exists kbuild does itDave Airlie
2006-10-14Add the missing breaks.Stephane Marchesin
2006-10-13Fix the fifo context size on nv10, nv20 and nv30.Stephane Marchesin
2006-10-14Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals)...Ben Skeggs
2006-10-12Oops.Stephane Marchesin
2006-10-12Still more work on the context switching code.Stephane Marchesin
2006-10-12Bugfixes.Thomas Hellstrom
2006-10-12Simplify the AGP backend interface somewhat.Thomas Hellstrom
2006-10-12More work on the context switch code. Still doesn't work. I'm mostly convince...Stephane Marchesin
2006-10-11Compatibility code for 2.6.15-2.6.18. It is ugly but a little comfort is thatThomas Hellstrom
2006-10-11Big update:Thomas Hellstrom
2006-10-11Context switching work.Stephane Marchesin
2006-10-10Use a nopage-based approach to fault in pfns.Thomas Hellstrom
2006-10-10only allow specific type-3 packets to pass the verifier instead of all for r1...Roland Scheidegger
2006-10-03Get rid of all ugly PTE hacks.Thomas Hellstrom
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #4.George Sapountzis
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #3.George Sapountzis
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #2.George Sapountzis
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #1.George Sapountzis
2006-10-02Bug 6209: [mach64] AGP DMA buffers not mapped correctly.George Sapountzis
2006-10-02Fix type of second argument to spin_lock_irqsave().Michel Dänzer
2006-10-02Fix type of second argument to spin_lock_irqsave().Michel Dänzer
2006-10-02Make the user_token 44-bit for TTMs, and have them occupy a unique file spaceThomas Hellstrom
2006-10-02Add a buffer object manager for TTM maps.Thomas Hellstrom
2006-10-02Allow for 44 bit user-tokens (or drm_file offsets)Thomas Hellstrom
2006-10-02Add a comment to previos commit.Thomas Hellstrom
2006-10-02Trap and be verbose about a deadlock that occurs with AIGLX and drivers thatThomas Hellstrom
2006-10-02drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.Felix Kühling
2006-10-02Make locked tasklet handling more robust.Michel Dänzer
2006-10-02drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.Felix Kühling
2006-09-29Bump driver date.Thomas Hellstrom
2006-09-29i915: Only schedule vblank tasklet if there are scheduled swaps pending.Michel Dänzer
2006-09-29i915: Only initialize IRQ fields in postinstall, not the PIPE_SET ioctl.Michel Dänzer
2006-09-29i915: Bump minor again to differentiate from vsync changes.Michel Dänzer
2006-09-29i915: Avoid mis-counting vblank interrupts when they're only enabled for pipe A.Michel Dänzer
2006-09-29i915: Bump minor for swap scheduling ioctl and secondary vblank support.Michel Dänzer
2006-09-29i915_vblank_swap: Add support for DRM_VBLANK_NEXTONMISS.Michel Dänzer
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-22 04:13:34 +0000
* paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Dave Mueller <dave.mueller@gmx.ch> * */ #include "dvo.h" /* register definitions according to the TFP410 data sheet */ #define TFP410_VID 0x014C #define TFP410_DID 0x0410 #define TFP410_VID_LO 0x00 #define TFP410_VID_HI 0x01 #define TFP410_DID_LO 0x02 #define TFP410_DID_HI 0x03 #define TFP410_REV 0x04 #define TFP410_CTL_1 0x08 #define TFP410_CTL_1_TDIS (1<<6) #define TFP410_CTL_1_VEN (1<<5) #define TFP410_CTL_1_HEN (1<<4) #define TFP410_CTL_1_DSEL (1<<3) #define TFP410_CTL_1_BSEL (1<<2) #define TFP410_CTL_1_EDGE (1<<1) #define TFP410_CTL_1_PD (1<<0) #define TFP410_CTL_2 0x09 #define TFP410_CTL_2_VLOW (1<<7) #define TFP410_CTL_2_MSEL_MASK (0x7<<4) #define TFP410_CTL_2_MSEL (1<<4) #define TFP410_CTL_2_TSEL (1<<3) #define TFP410_CTL_2_RSEN (1<<2) #define TFP410_CTL_2_HTPLG (1<<1) #define TFP410_CTL_2_MDI (1<<0) #define TFP410_CTL_3 0x0A #define TFP410_CTL_3_DK_MASK (0x7<<5) #define TFP410_CTL_3_DK (1<<5) #define TFP410_CTL_3_DKEN (1<<4) #define TFP410_CTL_3_CTL_MASK (0x7<<1) #define TFP410_CTL_3_CTL (1<<1) #define TFP410_USERCFG 0x0B #define TFP410_DE_DLY 0x32 #define TFP410_DE_CTL 0x33 #define TFP410_DE_CTL_DEGEN (1<<6) #define TFP410_DE_CTL_VSPOL (1<<5) #define TFP410_DE_CTL_HSPOL (1<<4) #define TFP410_DE_CTL_DEDLY8 (1<<0) #define TFP410_DE_TOP 0x34 #define TFP410_DE_CNT_LO 0x36 #define TFP410_DE_CNT_HI 0x37 #define TFP410_DE_LIN_LO 0x38 #define TFP410_DE_LIN_HI 0x39 #define TFP410_H_RES_LO 0x3A #define TFP410_H_RES_HI 0x3B #define TFP410_V_RES_LO 0x3C #define TFP410_V_RES_HI 0x3D struct tfp410_save_rec { uint8_t ctl1; uint8_t ctl2; }; struct tfp410_priv { bool quiet; struct tfp410_save_rec saved_reg; struct tfp410_save_rec mode_reg; }; static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) { struct tfp410_priv *tfp = dvo->dev_priv; struct intel_i2c_chan *i2cbus = dvo->i2c_bus; u8 out_buf[2]; u8 in_buf[2]; struct i2c_msg msgs[] = { { .addr = i2cbus->slave_addr, .flags = 0, .len = 1, .buf = out_buf, }, { .addr = i2cbus->slave_addr, .flags = I2C_M_RD, .len = 1, .buf = in_buf, } }; out_buf[0] = addr; out_buf[1] = 0; if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) { *ch = in_buf[0]; return true; }; if (!tfp->quiet) { DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", addr, i2cbus->adapter.name, i2cbus->slave_addr); } return false; } static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) { struct tfp410_priv *tfp = dvo->dev_priv; struct intel_i2c_chan *i2cbus = dvo->i2c_bus; uint8_t out_buf[2]; struct i2c_msg msg = { .addr = i2cbus->slave_addr, .flags = 0, .len = 2, .buf = out_buf, }; out_buf[0] = addr; out_buf[1] = ch; if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) return true; if (!tfp->quiet) { DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", addr, i2cbus->adapter.name, i2cbus->slave_addr); } return false; } static int tfp410_getid(struct intel_dvo_device *dvo, int addr) { uint8_t ch1, ch2; if (tfp410_readb(dvo, addr+0, &ch1) && tfp410_readb(dvo, addr+1, &ch2)) return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF); return -1; } /* Ti TFP410 driver for chip on i2c bus */ static bool tfp410_init(struct intel_dvo_device *dvo, struct intel_i2c_chan *i2cbus) { /* this will detect the tfp410 chip on the specified i2c bus */ struct tfp410_priv *tfp; int id; tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL); if (tfp == NULL) return false; dvo->i2c_bus = i2cbus; dvo->i2c_bus->slave_addr = dvo->slave_addr; dvo->dev_priv = tfp; tfp->quiet = true; if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n", id, i2cbus->adapter.name, i2cbus->slave_addr); goto out; } if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { DRM_DEBUG("tfp410 not detected got DID %X: from %s Slave %d.\n", id, i2cbus->adapter.name, i2cbus->slave_addr); goto out; } tfp->quiet = false; return true; out: kfree(tfp); return false; } static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo) { enum drm_connector_status ret = connector_status_disconnected; uint8_t ctl2; if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { if (ctl2 & TFP410_CTL_2_HTPLG) ret = connector_status_connected; else ret = connector_status_disconnected; } return ret; } static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo, struct drm_display_mode *mode) { return MODE_OK; } static void tfp410_mode_set(struct intel_dvo_device *dvo, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { /* As long as the basics are set up, since we don't have clock dependencies * in the mode setup, we can just leave the registers alone and everything * will work fine. */ /* don't do much */ return; } /* set the tfp410 power state */ static void tfp410_dpms(struct intel_dvo_device *dvo, int mode) { uint8_t ctl1; if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1)) return; if (mode == DRM_MODE_DPMS_ON) ctl1 |= TFP410_CTL_1_PD; else ctl1 &= ~TFP410_CTL_1_PD; tfp410_writeb(dvo, TFP410_CTL_1, ctl1); } static void tfp410_dump_regs(struct intel_dvo_device *dvo) { uint8_t val, val2; tfp410_readb(dvo, TFP410_REV, &val); DRM_DEBUG("TFP410_REV: 0x%02X\n", val); tfp410_readb(dvo, TFP410_CTL_1, &val); DRM_DEBUG("TFP410_CTL1: 0x%02X\n", val); tfp410_readb(dvo, TFP410_CTL_2, &val); DRM_DEBUG("TFP410_CTL2: 0x%02X\n", val); tfp410_readb(dvo, TFP410_CTL_3, &val); DRM_DEBUG("TFP410_CTL3: 0x%02X\n", val); tfp410_readb(dvo, TFP410_USERCFG, &val); DRM_DEBUG("TFP410_USERCFG: 0x%02X\n", val); tfp410_readb(dvo, TFP410_DE_DLY, &val); DRM_DEBUG("TFP410_DE_DLY: 0x%02X\n", val); tfp410_readb(dvo, TFP410_DE_CTL, &val); DRM_DEBUG("TFP410_DE_CTL: 0x%02X\n", val); tfp410_readb(dvo, TFP410_DE_TOP, &val); DRM_DEBUG("TFP410_DE_TOP: 0x%02X\n", val); tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); DRM_DEBUG("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); DRM_DEBUG("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); tfp410_readb(dvo, TFP410_H_RES_LO, &val); tfp410_readb(dvo, TFP410_H_RES_HI, &val2); DRM_DEBUG("TFP410_H_RES: 0x%02X%02X\n", val2, val); tfp410_readb(dvo, TFP410_V_RES_LO, &val); tfp410_readb(dvo, TFP410_V_RES_HI, &val2); DRM_DEBUG("TFP410_V_RES: 0x%02X%02X\n", val2, val); } static void tfp410_save(struct intel_dvo_device *dvo) { struct tfp410_priv *tfp = dvo->dev_priv; if (!tfp410_readb(dvo, TFP410_CTL_1, &tfp->saved_reg.ctl1)) return; if (!tfp410_readb(dvo, TFP410_CTL_2, &tfp->saved_reg.ctl2)) return; } static void tfp410_restore(struct intel_dvo_device *dvo) { struct tfp410_priv *tfp = dvo->dev_priv; /* Restore it powered down initially */ tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1 & ~0x1); tfp410_writeb(dvo, TFP410_CTL_2, tfp->saved_reg.ctl2); tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1); } static void tfp410_destroy(struct intel_dvo_device *dvo) { struct tfp410_priv *tfp = dvo->dev_priv; if (tfp) { kfree(tfp); dvo->dev_priv = NULL; } } struct intel_dvo_dev_ops tfp410_ops = { .init = tfp410_init, .detect = tfp410_detect, .mode_valid = tfp410_mode_valid, .mode_set = tfp410_mode_set, .dpms = tfp410_dpms, .dump_regs = tfp410_dump_regs, .save = tfp410_save, .restore = tfp410_restore, .destroy = tfp410_destroy, };
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-22 04:13:34 +0000