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2004-04-10white space changes to align with kernelDave Airlie
2004-04-10include highmem.hDave Airlie
2004-04-10update gamma_dma with patch from davej in 2.6Dave Airlie
2004-04-10patch from Andrew Morton tree from Arjan van de Ven fixes some oopses seenDave Airlie
with 4G/4G split
2004-04-10align code with Linux kernel.Dave Airlie
2004-04-10remove unused codeDave Airlie
2004-04-10update from linux kernel for ia64Dave Airlie
2004-04-09remove ImakefileAlan Hourihane
2004-04-08fix build problemAlan Hourihane
2004-04-08disable PCI DMA ioctls as they are not used currently until SAVAGE_CMD_DMAAlan Hourihane
is made to work.
2004-04-08big whitespace .. this aligns all the whitespace in this file with the bkDave Airlie
checkout linux tree
2004-04-082.6 sysfs patches + stubs in drmP.h for 2.4 compatibilityDave Airlie
2004-04-08long dev_t patches from 2.6 treeDave Airlie
2004-04-082.6 patches for larger dev_tDave Airlie
2004-04-08more 2.4 compat fnsDave Airlie
2004-04-08patch from Linux kernel 2.6.5Dave Airlie
2004-04-08fixes from Linux kernelDave Airlie
2004-04-08patch from lkDave Airlie
2004-03-31VIA module fixes:Thomas Hellstrom
1. Fixed up PCI-id's. 2. Fixed 2.6 warning in kernel Makefile.
2004-03-26copy correct MakefileDave Airlie
2004-03-26Added via driver to drm/linux/Config.in Reported by: Terry BarnabyThomas Hellstrom
2004-03-24Exported symbols cause compilation failure of via_mm.c on 2.4 kernels.Thomas Hellstrom
Added via_mm.o to export-objs: Reported by: HMX, Via Arena Forum
2004-03-24Modified linux/Kconfig to include the via drm driver.Thomas Hellstrom
2004-03-23Merged via-1-2-0: Altered Makefiles in drm/linuxThomas Hellstrom
2004-03-23Merged via-1-2-0Thomas Hellstrom
2004-03-23make sure in DRM toplevelDave Airlie
2004-03-23initial shell script to create linux kernel drm from the DRI oneDave Airlie
2004-03-17Adjust shared path in makefile XFree86 bug: Reported by: Submitted by:Jon Smirl
Reviewed by: Obtained from:
2004-03-16Makefile the makefile really clean everything XFree86 bug: Reported by:Jon Smirl
Submitted by: Reviewed by: Obtained from:
2004-03-16Add a missing ifdef CTX to get rid of the waring in the gamma driver build.Jon Smirl
XFree86 bug: Reported by: Submitted by: Reviewed by: Obtained from:
2004-03-12Fixes need to clean up the mess I made with the mesa merge. This codeJon Smirl
allows the mesa drivers to use a single definition of the DRM sarea/IOCTLS located in the drm driver directory. Adjustments were made to the 2D drivers to not include these changes. Changes to the mesa copy of DRM were copied to the DRI copy. XFree86 bug: Reported by: Submitted by: Reviewed by: Obtained from:
2004-02-28Remove extraneous code accidentally added with revision 1.86Michel Daenzer
2004-02-28More differentiated error codes for DRM(agp_acquire)Michel Daenzer
Obtained from: Linux kernel
2004-02-24Use DO_MUNMAP_4_ARGS macro defined in Makefile.linux (Steve Holland).Felix Kuehling
Silence a warning about a format-argument mismatch in printk.
2004-02-22Merged the Savage DRM driver from the savage-2-0-0-branch into the trunk.Felix Kuehling
2004-02-21Conditionally add definition of list_for_each_entry_safe for kernelFelix Kuehling
versions that don't have it.
2004-02-20drm_ctx_dtor.patch Submitted by: Erdi ChenKeith Whitwell
2004-02-18Fix sisfb header location for 2.6 kernelsMichel Daenzer
Submitted by: Andrew Morton
2004-01-11Adapt to nopage() prototype change in Linux 2.6.1.Michel Daenzer
Reviewed by: Arjan van de Ven <arjanv@redhat.com>, additional feedback from William Lee Irwin III and Linus Torvalds.
2004-01-10Make sure that all state packets are handled inMichel Daenzer
radeon_check_and_fixup_packets() Fix state packet IDs of R200 cubic offsets
2004-01-10R200_PP_CUBIC_OFFSET_F1_[0-6] state packets only contain 5 offsets, not 6Michel Daenzer
(thanks to Andreas Stenglein for spotting this)
2004-01-06Fix some misuse of NULL where 0 is intended.Eric Anholt
Obtained from: FreeBSD CVS
2003-12-16Don't ioremap the framebuffer area. The ioremapped area wasn't used byEric Anholt
anything, and took up valuable KVA. While I'm in the area, clean up BSD MTRR stuff some more. Suggested by: jonsmirl
2003-12-16Add a collection of Radeon and R128 PCI IDs, including the IGP chipsets.Eric Anholt
Submitted by: Donnie Berkholz <spyderous@gentoo.org> (mostly)
2003-12-08Add i865 pci idKeith Whitwell
2003-11-12Fix a locking nit, and add asserts in some things that should be calledEric Anholt
with locks held.
2003-11-06Return EBUSY when attempting to addmap a DRM_SHM area with a lock in it ifEric Anholt
dev->lock.hw_lock is already set. This fixes the case of two X Servers running on the same head on different VTs with interface 1.1, by making the 2nd head fail to inizialize like before.
2003-11-06Remove unused variable.Eric Anholt
2003-11-05Changes to DRM(irq_install)...... wrap dev->dma usage with __HAVE_DMA inAlan Hourihane
irq handler, fixes kernel ooops. comment out some setting of flags that are done in DRM(setup) (not sure why both of the above is done in the irq handler)
2003-11-05- Tie the DRM to a specific device: setunique no longer succeeds when givenEric Anholt
a busid that doesn't correspond to the device the DRM is attached to. This is a breaking of backwards-compatibility only for the multiple-DRI-head case with X Servers that don't use interface 1.1. - Move irq_busid to drm_irq.h and make it only return the IRQ for the current device. Retains compatibility with previous X Servers, cleans up unnecessary code. This means no irq_busid on !__HAVE_IRQ, but can be changed if necessary. - Bump interface version to 1.2. This version when set signifies that the control ioctl should ignore the irq number passed in and enable the interrupt handler for the attached device. Otherwise it errors out when the passed-in irq is not equal to the device's. - Store the highest version the interface has been set to in the device. - Fix a recursion on DRM_LOCK in irq_uninstall on FreeBSD. This leaves irq_uninstall being done without the lock in some cases, but it was racey anyways.
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 13:48:45 +0000
pan> #define MGA_UPLOAD_2D 0x40 #define MGA_WAIT_AGE 0x80 /* handled client-side */ #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ #if 0 #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock quiescent */ #endif /* 32 buffers of 64k each, total 2 meg. */ #define MGA_BUFFER_SIZE (1 << 16) #define MGA_NUM_BUFFERS 128 /* Keep these small for testing. */ #define MGA_NR_SAREA_CLIPRECTS 8 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128 * regions, subject to a minimum region size of (1<<16) == 64k. * * Clients may subdivide regions internally, but when sharing between * clients, the region size is the minimum granularity. */ #define MGA_CARD_HEAP 0 #define MGA_AGP_HEAP 1 #define MGA_NR_TEX_HEAPS 2 #define MGA_NR_TEX_REGIONS 16 #define MGA_LOG_MIN_TEX_REGION_SIZE 16 #define DRM_MGA_IDLE_RETRY 2048 #endif /* __MGA_SAREA_DEFINES__ */ /* Setup registers for 3D context */ typedef struct { unsigned int dstorg; unsigned int maccess; unsigned int plnwt; unsigned int dwgctl; unsigned int alphactrl; unsigned int fogcolor; unsigned int wflag; unsigned int tdualstage0; unsigned int tdualstage1; unsigned int fcol; unsigned int stencil; unsigned int stencilctl; } drm_mga_context_regs_t; /* Setup registers for 2D, X server */ typedef struct { unsigned int pitch; } drm_mga_server_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int texctl; unsigned int texctl2; unsigned int texfilter; unsigned int texbordercol; unsigned int texorg; unsigned int texwidth; unsigned int texheight; unsigned int texorg1; unsigned int texorg2; unsigned int texorg3; unsigned int texorg4; } drm_mga_texture_regs_t; /* General aging mechanism */ typedef struct { unsigned int head; /* Position of head pointer */ unsigned int wrap; /* Primary DMA wrap count */ } drm_mga_age_t; typedef struct _drm_mga_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ drm_mga_context_regs_t context_state; drm_mga_server_regs_t server_state; drm_mga_texture_regs_t tex_state[2]; unsigned int warp_pipe; unsigned int dirty; unsigned int vertsize; /* The current cliprects, or a subset thereof. */ struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Information about the most recently used 3d drawable. The * client fills in the req_* fields, the server fills in the * exported_ fields and puts the cliprects into boxes, above. * * The client clears the exported_drawable field before * clobbering the boxes data. */ unsigned int req_drawable; /* the X drawable id */ unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ unsigned int exported_drawable; unsigned int exported_index; unsigned int exported_stamp; unsigned int exported_buffers; unsigned int exported_nfront; unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ unsigned int status[4]; unsigned int last_wrap; drm_mga_age_t last_frame; unsigned int last_enqueue; /* last time a buffer was enqueued */ unsigned int last_dispatch; /* age of the most recently dispatched buffer */ unsigned int last_quiescent; /* */ /* LRU lists for texture memory in agp space and on the card. */ struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; unsigned int texAge[MGA_NR_TEX_HEAPS]; /* Mechanism to validate card state. */ int ctxOwner; } drm_mga_sarea_t; /* MGA specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_MGA_INIT 0x00 #define DRM_MGA_FLUSH 0x01 #define DRM_MGA_RESET 0x02 #define DRM_MGA_SWAP 0x03 #define DRM_MGA_CLEAR 0x04 #define DRM_MGA_VERTEX 0x05 #define DRM_MGA_INDICES 0x06 #define DRM_MGA_ILOAD 0x07 #define DRM_MGA_BLIT 0x08 #define DRM_MGA_GETPARAM 0x09 /* 3.2: * ioctls for operating on fences. */ #define DRM_MGA_SET_FENCE 0x0a #define DRM_MGA_WAIT_FENCE 0x0b #define DRM_MGA_DMA_BOOTSTRAP 0x0c #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) typedef struct _drm_mga_warp_index { int installed; unsigned long phys_addr; int size; } drm_mga_warp_index_t; typedef struct drm_mga_init { enum { MGA_INIT_DMA = 0x01, MGA_CLEANUP_DMA = 0x02 } func; unsigned long sarea_priv_offset; int chipset; int sgram; unsigned int maccess; unsigned int fb_cpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_cpp; unsigned int depth_offset, depth_pitch; unsigned int texture_offset[MGA_NR_TEX_HEAPS]; unsigned int texture_size[MGA_NR_TEX_HEAPS]; unsigned long fb_offset; unsigned long mmio_offset; unsigned long status_offset; unsigned long warp_offset; unsigned long primary_offset; unsigned long buffers_offset; } drm_mga_init_t; typedef struct drm_mga_dma_bootstrap { /** * \name AGP texture region * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will * be filled in with the actual AGP texture settings. * * \warning * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode * is zero, it means that PCI memory (most likely through the use of * an IOMMU) is being used for "AGP" textures. */ /*@{*/ unsigned long texture_handle; /**< Handle used to map AGP textures. */ uint32_t texture_size; /**< Size of the AGP texture region. */ /*@}*/ /** * Requested size of the primary DMA region. * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual AGP mode. If AGP was not available */ uint32_t primary_size; /** * Requested number of secondary DMA buffers. * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual number of secondary DMA buffers * allocated. Particularly when PCI DMA is used, this may be * (subtantially) less than the number requested. */ uint32_t secondary_bin_count; /** * Requested size of each secondary DMA buffer. * * While the kernel \b is free to reduce * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed * to reduce dma_mga_dma_bootstrap::secondary_bin_size. */ uint32_t secondary_bin_size; /** * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is * zero, it means that PCI DMA should be used, even if AGP is * possible. * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual AGP mode. If AGP was not available * (i.e., PCI DMA was used), this value will be zero. */ uint32_t agp_mode; /** * Desired AGP GART size, measured in megabytes. */ uint8_t agp_size; } drm_mga_dma_bootstrap_t; typedef struct drm_mga_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; } drm_mga_clear_t; typedef struct drm_mga_vertex { int idx; /* buffer to queue */ int used; /* bytes in use */ int discard; /* client finished with buffer? */ } drm_mga_vertex_t; typedef struct drm_mga_indices { int idx; /* buffer to queue */ unsigned int start; unsigned int end; int discard; /* client finished with buffer? */ } drm_mga_indices_t; typedef struct drm_mga_iload { int idx; unsigned int dstorg; unsigned int length; } drm_mga_iload_t; typedef struct _drm_mga_blit { unsigned int planemask; unsigned int srcorg; unsigned int dstorg; int src_pitch, dst_pitch; int delta_sx, delta_sy; int delta_dx, delta_dy; int height, ydir; /* flip image vertically */ int source_pitch, dest_pitch; } drm_mga_blit_t; /* 3.1: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define MGA_PARAM_IRQ_NR 1 /* 3.2: Query the actual card type. The DDX only distinguishes between * G200 chips and non-G200 chips, which it calls G400. It turns out that * there are some very sublte differences between the G4x0 chips and the G550