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2006-09-28Core vsync: Add flag DRM_VBLANK_NEXTONMISS.Michel Dänzer
When this flag is set and the target sequence is missed, wait for the next vertical blank instead of returning immediately.
2006-09-28Fix 'sequence has passed' condition in i915_vblank_swap().Michel Dänzer
2006-09-28Add SAREA fileds for determining which pipe to sync window buffer swaps to.Michel Dänzer
2006-09-28Add definition of DRM_VBLANK_SECONDARY.Michel Dänzer
2006-09-28Make handling of dev_priv->vblank_pipe more robust.Michel Dänzer
Initialize it to default value if it hasn't been set by the X server yet. In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call i915_enable_interrupt() if the argument passed from userspace is valid to avoid corrupting dev_priv->vblank_pipe on invalid arguments.
2006-09-28DRM_I915_VBLANK_SWAP ioctl: Take drm_vblank_seq_type_t instead of pipe number.Michel Dänzer
Handle relative as well as absolute target sequence numbers. Return error if target sequence has already passed, so userspace can deal with this situation as it sees fit. On success, return the sequence number of the vertical blank when the buffer swap is expected to take place. Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want to use ioctl() instead of drmCommandWriteRead().
2006-09-28Change first valid DRM drawable ID to be 1 instead of 0.Michel Dänzer
This makes it easier for userspace to know when it needs to allocate an ID. Also free drawable information memory when it's no longer needed.
2006-09-28Add copyright notice.Michel Dänzer
2006-09-28i915: Add ioctl for scheduling buffer swaps at vertical blanks.Michel Dänzer
This uses the core facility to schedule a driver callback that will be called ASAP after the given vertical blank interrupt with the HW lock held.
2006-09-28Locking and memory management fixes.Michel Dänzer
2006-09-28Drop tasklet locked driver callback when uninstalling IRQ.Michel Dänzer
2006-09-28Export drm_get_drawable_info symbol from core.Michel Dänzer
2006-09-28Hook up DRM_IOCTL_UPDATE_DRAW ioctl.Michel Dänzer
2006-09-28Only reallocate cliprect memory if the number of cliprects changes.Michel Dänzer
Also improve diagnostic output.
2006-09-28Add support for tracking drawable information to coreMichel Dänzer
Actually make the existing ioctls for adding and removing drawables do something useful, and add another ioctl for the X server to update drawable information. The only kind of drawable information tracked so far is cliprects.
2006-09-28Add support for interrupt triggered driver callback with lock held to DRM core.Michel Dänzer
2006-09-28Add support for secondary vertical blank interrupt to i915 driver.Michel Dänzer
When the vertical blank interrupt is enabled for both pipes, pipe A is considered primary and pipe B secondary. When it's only enabled for one pipe, it's always considered primary for backwards compatibility.
2006-09-28Add support for secondary vertical blank interrupt to DRM core.Michel Dänzer
2006-09-28Libdrm version bump and naming.Thomas Hellstrom
2006-09-28Don't enable fence / buffer objects on non-linux systems.Thomas Hellstrom
Bump driver minor and date.
2006-09-27Activate error message that was never hit since it was maskedThomas Hellstrom
by drm_lock_transfer. Ifdef out drm_lock_transfer. I see no use for it currently. Should be removed.
2006-09-27Fix racy buffer object destruction.Thomas Hellstrom
2006-09-27Fix tt fixed size that slipped through in previous commit.Thomas Hellstrom
2006-09-27Adapt to architecture-specific hooks for gatt pages.Thomas Hellstrom
2006-09-26Silence valgrind.Thomas Hellstrom
2006-09-26Remove the call to drm_lock_transfer, since it is not used anymore.Thomas Hellstrom
Fix up drm_lock_free to retain the last locking context information.
2006-09-26Allow for a driver to overload the ttm backend object methods.Thomas Hellstrom
2006-09-25Add /proc filesystem buffer / fence object accounting.Thomas Hellstrom
Check for NULL pointer in the i915 flush handler. Remove i915_sync_flush declaration.
2006-09-22Fix proc formatting broken by last commit.Thomas Hellstrom
GPU lockup error reporting.
2006-09-22bug 5942: add stubs for drm_mtrr_add/del for non-MTRR configured linuxFelix Kuhling
2006-09-22bug 7092 : add pci ids for mach64 in Dell poweredge 4200Anish Mistry
2006-09-20do a TCL state flush before accessing VAP_CNTL to prevent lockups on r200 ↵Roland Scheidegger
when enabling/disabling vertex programs
2006-09-20Allow for 64-bit map handles of ttms and buffer objects.Thomas Hellstrom
2006-09-18Fence handler fixThomas Hellstrom
2006-09-18Alternative implementation of page table zeroing using zap page_range.Thomas Hellstrom
(Disabled for now) Fix bo_wait_idle bug. Remove stray debug message.
2006-09-18More verbose error reporting in some cases.Thomas Hellstrom
Add a buffer object waitIdle user-space function. Fix some names and minor glitches.
2006-09-18drm: put domain number back to 0, domain support is seriously fubar..Dave Airlie
2006-09-17Add pciid for GeForce Go 6150 (0x0244).Ben Skeggs
2006-09-15Use register writes instead of BITBLT_MULTI packets for buffer swap blits.Michel Dänzer
This takes up two more ring buffer entries per rectangle blitted but makes sure the blit is performed top to bottom, reducing the likelyhood of tearing.
2006-09-15Allow a "native type" to be associated with a fence sequence.Thomas Hellstrom
In the intel case, we can associate a flush with a sequence.
2006-09-15Some bugfixes.Thomas Hellstrom
Change the fence object interface somewhat to allow some more flexibility. Make list IOCTLS really restartable. Try to avoid busy-waits in the kernel using immediate return to user-space with an -EAGAIN.
2006-09-14Simplify ttm alloc and free.Thomas Hellstrom
2006-09-14Remove the use of reserved pages, and use locked pages instead.Thomas Hellstrom
Update compatibility for latest linux versions.
2006-09-12Fix some debug messages.Thomas Hellstrom
2006-09-12Use lazy fence wait when possible even for RW fences. Saves some CPU.Thomas Hellstrom
Lindent.
2006-09-12More bugfixes.Thomas Hellstrom
Disable the i915 IRQ turnoff for now since it seems to be causing problems.
2006-09-12drm: use radeon specific names for radeon flagsDave Airlie
2006-09-09Add copyright notices while I still remember..Ben Skeggs
2006-09-08Various bugfixes.Thomas Hellstrom
2006-09-07Fix second start of X server without module reload beforehand, and a couple ↵Ben Skeggs
of other fixes. - Mark the correct RAMIN slots as free (oops) - Remove a VRAM alloc that shouldn't have been there (oops) - Move HT init out of firstopen() and into dma_init() - Setup PFIFO_RAM{HT,FC,RO} in pfifo_init()
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 11:50:04 +0000
class="hl com">/* _I830_DEFINES_ */ typedef struct _drm_i830_init { enum { I830_INIT_DMA = 0x01, I830_CLEANUP_DMA = 0x02 } func; unsigned int mmio_offset; unsigned int buffers_offset; int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; unsigned int back_pitch; unsigned int depth_pitch; unsigned int cpp; } drm_i830_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i830_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i830_tex_region_t; typedef struct _drm_i830_sarea { unsigned int ContextState[I830_CTX_SETUP_SIZE]; unsigned int BufferState[I830_DEST_SETUP_SIZE]; unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; unsigned int Palette[2][256]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ int perf_boxes; /* performance boxes to be displayed */ /* Here's the state for texunits 2,3: */ unsigned int TexState2[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed2; unsigned int TexState3[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState3[I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed3; unsigned int StippleState[I830_STP_SETUP_SIZE]; } drm_i830_sarea_t; /* Flags for perf_boxes */ #define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ #define I830_BOX_FLIP 0x2 /* populated by kernel */ #define I830_BOX_WAIT 0x4 /* populated by kernel & client */ #define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ #define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ /* I830 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) #define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) #define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) #define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) #define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) #define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) #define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) #define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) #define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) #define DRM_IOCTL_I830_FLIP DRM_IO ( 0x49) #define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(0x4a, drm_i830_irq_emit_t) #define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( 0x4b, drm_i830_irq_wait_t) #define DRM_IOCTL_I830_GETPARAM DRM_IOWR(0x4c, drm_i830_getparam_t) #define DRM_IOCTL_I830_SETPARAM DRM_IOWR(0x4d, drm_i830_setparam_t) typedef struct _drm_i830_clear { int clear_color; int clear_depth; int flags; unsigned int clear_colormask; unsigned int clear_depthmask; } drm_i830_clear_t; /* These may be placeholders if we have more cliprects than * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i830_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i830_vertex_t; typedef struct _drm_i830_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void __user *address; /* Address to copy from */ } drm_i830_copy_t; typedef struct drm_i830_dma { void __user *virtual; int request_idx; int request_size; int granted; } drm_i830_dma_t; /* 1.3: Userspace can request & wait on irq's: */ typedef struct drm_i830_irq_emit { int __user *irq_seq; } drm_i830_irq_emit_t; typedef struct drm_i830_irq_wait { int irq_seq; } drm_i830_irq_wait_t; /* 1.3: New ioctl to query kernel params: */ #define I830_PARAM_IRQ_ACTIVE 1 typedef struct drm_i830_getparam { int param; int __user *value; } drm_i830_getparam_t; /* 1.3: New ioctl to set kernel params: */ #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 typedef struct drm_i830_setparam { int param; int value; } drm_i830_setparam_t; #endif /* _I830_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 11:50:03 +0000