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2007-07-18Fix via dmablit when blit queue is full.Thomas Hellstrom
Fix by Simon Farnsworth, Bugzilla Bug #11542 http://bugs.freedesktop.org/show_bug.cgi?id=11542
2007-07-18fix some missing whitespace/tabDave Airlie
2007-07-18drm: idr stuff is upstream for 2.6.23Dave Airlie
2007-07-18drm: remove drm_u64_t, replace with uint64_t everwhereDave Airlie
This might break something, stdint.h inclusion in drm.h maybe required but I'm not sure yet what platforms have it what ones don't.
2007-07-18drm_context: fix brainoDave Airlie
2007-07-16Add XP5 and XP10 PCI IDs.Ian Romanick
2007-07-16Make drm_sg_free callable in-kernel.Ian Romanick
2007-07-16Log message clean up in WriteRegDWord. Remove unused inline functions.Ian Romanick
2007-07-16Clean ups (primarilly log messages) in xgi_test_rwinkernel.Ian Romanick
2007-07-16Eliminate unnecessary structures and defines.Ian Romanick
2007-07-17nouveau: Destroy PGRAPH context table on PGRAPH takedownBen Skeggs
2007-07-16Eliminate several useless ioctls and associated cruft.Ian Romanick
The ioctlss XGI_ESC_DEVICE_INFO, XGI_ESC_MEM_COLLECT, XGI_ESC_PCIE_CHECK, XGI_ESC_GET_SCREEN_INFO, XGI_ESC_PUT_SCREEN_INFO, XGI_ESC_MMIO_INFO, and XGI_ESC_SAREA_INFO, are completely unnecessary. The will be doubly useless when the driver is converted to the DRM infrastructure.
2007-07-16Massive log message clean up in xgi_submit_cmdlist.Ian Romanick
2007-07-17nouveau: G8x PCIEGARTBen Skeggs
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
2007-07-16Correct errors in the usage of pci_map_page.Ian Romanick
With these changes the driver no longer instantly hard-locks a 6600LE on a PowerPC G5. I haven't tested any 3D apps yet.
2007-07-16Fix FreeBSD build.Eric Anholt
2007-07-16drm/radeon/ttm: more VRAM fixesDave Airlie
2007-07-16drm: fixup old kernel compat codeDave Airlie
2007-07-16drm: fixup compat wrappersDave Airlie
2007-07-16drm: remove internal sman typedefDave Airlie
2007-07-16drm: remove drm_ref_tDave Airlie
2007-07-16drm: remove drm_buf_tDave Airlie
2007-07-16drm: detypedef ttm/bo/fence codeDave Airlie
2007-07-16drm: remove hashtab/sman and object typedefsDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-07-16drm: remove ttm userspace typedefsDave Airlie
2007-07-16drm: detypedef drm.h and fixup all problemsDave Airlie
2007-07-16drm: fix typedef in drm_os_linux.hDave Airlie
2007-07-16drm: remove typedefs in drm.h to their own sectionDave Airlie
2007-07-16Merge branch 'drm-ttm-cleanup-branch'Dave Airlie
2007-07-14nouveau: nv10 and nv11/15 are differentPatrice Mandin
2007-07-13applied patch from Ian Romanick fixing PCI DMA object creation codeArthur Huillet
2007-07-13Merge commit 'public/master'Arthur Huillet
2007-07-13now attempting to create PCI object only when there is a pci_heapArthur Huillet
2007-07-13now attempting to create PCI object only when there is a pci_heapArthur Huillet
2007-07-13nouveau: nuke internal typedefs, and drm_device_t use.Ben Skeggs
2007-07-12Merge branch 'master' into xgi-0-0-2Ian Romanick
2007-07-13nouveau: unbreak AGPBen Skeggs
2007-07-12radeon: add VRAM support for radeon ttmDave Airlie
This needs a lot of testing
2007-07-12Merge branch 'radeon-ttm' of git://people.freedesktop.org/~airlied/drm into ↵Dave Airlie
radeon-ttm Conflicts: linux-core/ati_pcigart.c linux-core/drmP.h linux-core/radeon_buffer.c
2007-07-12nouveau: mem_alloc() returns offsets, not absolute addresses now.Ben Skeggs
2007-07-12nouveau: nuke left over debug messageBen Skeggs
2007-07-12nouveau: separate region_offset into map_handle and offset.Ben Skeggs
2007-07-12fixed object creation code to not Oops on 64bits, worked around memalloc not ↵Arthur Huillet
working on 64bit for PCIGART
2007-07-11NV50 will not attempt to use PCIGART nowArthur Huillet
2007-07-11fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵Arthur Huillet
probably still have a problem
2007-07-11nouveau/nv50: G80 fixes.Ben Skeggs
Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11nouveau: Some checks on userspace object handles.Ben Skeggs
2007-07-11Merge branch 'master' into cleanupDave Airlie
Conflicts: libdrm/xf86drm.c linux-core/drm_bo.c linux-core/drm_fence.c
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 10:56:33 +0000
l kwd">get_batch_command(enum xgi_batch_type type) { static const unsigned int ports[4] = { 0x30 >> 2, 0x40 >> 2, 0x50 >> 2, 0x20 >> 2 }; return ports[type]; } int xgi_submit_cmdlist(struct drm_device * dev, void * data, struct drm_file * filp) { struct xgi_info *const info = dev->dev_private; const struct xgi_cmd_info *const pCmdInfo = (struct xgi_cmd_info *) data; const unsigned int cmd = get_batch_command(pCmdInfo->type); u32 begin[4]; begin[0] = (cmd << 24) | BEGIN_VALID_MASK | (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence); begin[1] = BEGIN_LINK_ENABLE_MASK | pCmdInfo->size; begin[2] = pCmdInfo->hw_addr >> 4; begin[3] = 0; if (info->cmdring.last_ptr == NULL) { const unsigned int portOffset = BASE_3D_ENG + (cmd << 2); /* Enable PCI Trigger Mode */ dwWriteReg(info->mmio_map, BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS, (M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | M2REG_CLEAR_COUNTERS_MASK | 0x08 | M2REG_PCI_TRIGGER_MODE_MASK); dwWriteReg(info->mmio_map, BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS, (M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 | M2REG_PCI_TRIGGER_MODE_MASK); /* Send PCI begin command */ dwWriteReg(info->mmio_map, portOffset, begin[0]); dwWriteReg(info->mmio_map, portOffset + 4, begin[1]); dwWriteReg(info->mmio_map, portOffset + 8, begin[2]); dwWriteReg(info->mmio_map, portOffset + 12, begin[3]); } else { DRM_DEBUG("info->cmdring.last_ptr != NULL\n"); if (pCmdInfo->type == BTYPE_3D) { xgi_emit_flush(info, FALSE); } info->cmdring.last_ptr[1] = cpu_to_le32(begin[1]); info->cmdring.last_ptr[2] = cpu_to_le32(begin[2]); info->cmdring.last_ptr[3] = cpu_to_le32(begin[3]); DRM_WRITEMEMORYBARRIER(); info->cmdring.last_ptr[0] = cpu_to_le32(begin[0]); triggerHWCommandList(info); } info->cmdring.last_ptr = xgi_find_pcie_virt(info, pCmdInfo->hw_addr); #ifdef XGI_HAVE_FENCE drm_fence_flush_old(info->dev, 0, info->next_sequence); #endif /* XGI_HAVE_FENCE */ return 0; } /* state: 0 - console 1 - graphic 2 - fb 3 - logout */ int xgi_state_change(struct xgi_info * info, unsigned int to, unsigned int from) { #define STATE_CONSOLE 0 #define STATE_GRAPHIC 1 #define STATE_FBTERM 2 #define STATE_LOGOUT 3 #define STATE_REBOOT 4 #define STATE_SHUTDOWN 5 if ((from == STATE_GRAPHIC) && (to == STATE_CONSOLE)) { DRM_INFO("Leaving graphical mode (probably VT switch)\n"); } else if ((from == STATE_CONSOLE) && (to == STATE_GRAPHIC)) { DRM_INFO("Entering graphical mode (probably VT switch)\n"); xgi_cmdlist_reset(info); } else if ((from == STATE_GRAPHIC) && ((to == STATE_LOGOUT) || (to == STATE_REBOOT) || (to == STATE_SHUTDOWN))) { DRM_INFO("Leaving graphical mode (probably X shutting down)\n"); } else { DRM_ERROR("Invalid state change.\n"); return -EINVAL; } return 0; } int xgi_state_change_ioctl(struct drm_device * dev, void * data, struct drm_file * filp) { struct xgi_state_info *const state = (struct xgi_state_info *) data; struct xgi_info *info = dev->dev_private; return xgi_state_change(info, state->_toState, state->_fromState); } void xgi_cmdlist_reset(struct xgi_info * info) { info->cmdring.last_ptr = NULL; info->cmdring.ring_offset = 0; } void xgi_cmdlist_cleanup(struct xgi_info * info) { if (info->cmdring.ring_hw_base != 0) { /* If command lists have been issued, terminate the command * list chain with a flush command. */ if (info->cmdring.last_ptr != NULL) { xgi_emit_flush(info, FALSE); xgi_emit_nop(info); } xgi_waitfor_pci_idle(info); (void) memset(&info->cmdring, 0, sizeof(info->cmdring)); } } static void triggerHWCommandList(struct xgi_info * info) { static unsigned int s_triggerID = 1; dwWriteReg(info->mmio_map, BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS, 0x05000000 + (0x0ffff & s_triggerID++)); } /** * Emit a flush to the CRTL command stream. * @info XGI info structure * * This function assumes info->cmdring.ptr is non-NULL. */ void xgi_emit_flush(struct xgi_info * info, bool stop) { const u32 flush_command[8] = { ((0x10 << 24) | (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence)), BEGIN_LINK_ENABLE_MASK | (0x00004), 0x00000000, 0x00000000, /* Flush the 2D engine with the default 32 clock delay. */ M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, }; const unsigned int flush_size = sizeof(flush_command); u32 *batch_addr; u32 hw_addr; unsigned int i; /* check buf is large enough to contain a new flush batch */ if ((info->cmdring.ring_offset + flush_size) >= info->cmdring.size) { info->cmdring.ring_offset = 0; } hw_addr = info->cmdring.ring_hw_base + info->cmdring.ring_offset; batch_addr = info->cmdring.ptr + (info->cmdring.ring_offset / 4); for (i = 0; i < (flush_size / 4); i++) { batch_addr[i] = cpu_to_le32(flush_command[i]); } if (stop) { *batch_addr |= cpu_to_le32(BEGIN_STOP_STORE_CURRENT_POINTER_MASK); } info->cmdring.last_ptr[1] = cpu_to_le32(BEGIN_LINK_ENABLE_MASK | (flush_size / 4)); info->cmdring.last_ptr[2] = cpu_to_le32(hw_addr >> 4); info->cmdring.last_ptr[3] = 0; DRM_WRITEMEMORYBARRIER(); info->cmdring.last_ptr[0] = cpu_to_le32((get_batch_command(BTYPE_CTRL) << 24) | (BEGIN_VALID_MASK));