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2008-05-21rs690/r500: vblank support.Dave Airlie
The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips
2008-05-20[gem] Use a separate sequence number field from classic/ttmEric Anholt
This lets us get some qualities we desire, such as using the full 32-bit range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active sequence numbers to request structs, which will be used soon for throttling and interrupt-driven list cleanup.
2008-05-20[gem] Rename sequence numbers from "cookie" to "seqno"Eric Anholt
2008-05-20[gem] Clean up active/inactive list handling using helper functions.Eric Anholt
Additionally, a boolean active field is added to indicate which list an object is on, rather than smashing last_rendering_cookie to 0 to show inactive. This will help with flush-reduction later on, and makes the code clearer.
2008-05-17r500: add more register ranges for Mesa driverDave Airlie
2008-05-15[gem] Hold dev->struct_mutex to protect structure data.Eric Anholt
2008-05-15[gem] Rename the GTT LRU lists to active (executing) and inactive (idle).Eric Anholt
2008-05-15[gem] typo fix in comment.Eric Anholt
2008-05-14ati_pcigart: oops wrong way around not that it actually matteredDave Airlie
2008-05-14ati_pcigart: stop working in the evenings you mess up too oftenDave Airlie
2008-05-14Revert "ati_pcigart: fixup properly this version might even work"Dave Airlie
This reverts commit bc0836e12a9790f1cc83f8bc29bc05043c4bc840. tree has some kref hacks in it - oops
2008-05-14ati_pcigart: fixup properly this version might even workDave Airlie
2008-05-14ati_pcigart: fill out 40-bit gart table support properlyDave Airlie
Thanks to Alex for supplying this info.
2008-05-13RS4xx: separate out RS400 and RS480 IGP chipsAlex Deucher
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
2008-05-13Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm ↵Jesse Barnes
into modesetting-101
2008-05-13i915: register definition & header file cleanupJesse Barnes
It would be nice if one day the DRM driver was the canonical source for register definitions and core macros. To that end, this patch cleans things up quite a bit, removing redundant definitions (some with different names referring to the same register) and generally tidying up the header file.
2008-05-13i915: execbuf now works without i915_dma_init being calledJakob Bornecrantz
2008-05-12i915: TV hotplug fixesJesse Barnes
In order to avoid recursive ->detect->interrupt->detect->interrupt->... we need to disable TV hotplug interrupts in intel_tv.c:intel_tv_detect_type. We also need to enable the TV interrupt detection and hotplug sequence properly in i915_irq.c.
2008-05-12[GEM] Update testcases for new API.Eric Anholt
2008-05-12[GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.Eric Anholt
2008-05-12[intel] Minor kludge -- wait for the ring to be nearly empty before queuingKeith Packard
No need to fill the ring that much; wait for it to become nearly empty before adding the execbuffer request. A better fix will involve scheduling ring insertion in the irq handler.
2008-05-12[intel] When polling for ring space, sleep for a lot longer (10ms)Keith Packard
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12[gem] Set write domain to CPU when doing pwrite.Keith Packard
Leave the flush call in place, which can fix domains up if necessary.
2008-05-12[gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage.Keith Packard
2008-05-12fix kernel oops when removing fbHong Liu
drm_crtc->fb may point to NULL, f.e X server will allocate a new fb and assign it to the CRTC at startup, when X server exits, it will destroy the allocated fb, making drm_crtc->fb points to NULL.
2008-05-12free dummy read page if fail to init mmHong Liu
Since drm_bo_driver_init will be called in driver_load, we need to free what it alloced when error to avoid memory leak.
2008-05-12modeset init code cleanupHong Liu
moving modeset init code into one function and correct error handling druing i915 init
2008-05-12fix G33 hardware status page in modesetHong Liu
We need to alloc a hw status page bo for G33 if modeset is enabled since the 2D driver can't alloc gfx memory when working in drm modeset.
2008-05-12RADEON: fix copy/pasto in last commitAlex Deucher
2008-05-12R3/4/5: init pipe setup in drmAlex Deucher
Similar (broken) code in mesa needs to be removed
2008-05-12RADEON: cleanup radeon_do_engine_reset()Alex Deucher
2008-05-12R300+: fixup pixcache flushAlex Deucher
2008-05-12RS4xx: fix MCIND index maskAlex Deucher
2008-05-12RADEON: write AGP_BASE_2 on chips that support itAlex Deucher
2008-05-12R300+: fixup PURGE/FLUSH macrosAlex Deucher
2008-05-12Radeon IGP: merge RS4xx/RS6xx gart setupAlex Deucher
2008-05-12Radeon IGP: wrap MCIND accessAlex Deucher
first step in merging rs4xx/rs6xx gart setup
2008-05-12Radeon IGP: clean up registers and magic numbersAlex Deucher
2008-05-12drm: remove root only from a lot of drm ioctls to get stuff running as non-rootDave Airlie
2008-05-12drm: masters are always authenticatedDave Airlie
2008-05-12drm: fix oops on reading proc file with no masterDave Airlie
2008-05-11[GEM] Make pread/pwrite manage memory domains. No luck with movnti though.Keith Packard
pread and pwrite must update the memory domains to ensure consistency with the GPU. At some point, it should be possible to avoid clflush through this path, but that isn't working for me.
2008-05-10[intel-GEM] exec list can contain pinned, lru cannot.Keith Packard
The exec list contains all objects, in order of use. The lru list contains only unpinned objects ready to be evicted. This required two changes -- the first was to not migrate pinned objects from exec to lru, the second was to search for the first unpinned object in the exec list when doing eviction.
2008-05-10Merge commit 'anholt/drm-gem' into drm-gemKeith Packard
2008-05-10[GEM] Add drm-gem.txtKeith Packard
Add some API and implementation documentation for GEM.
2008-05-10[intel-GEM] Clean up GEM ioctl naming.Keith Packard
Rename 'validate_entry' to 'exec_object', then clean up some field names in structures (renaming buffer_offset to just offset, for example).
2008-05-09GEM: Fix arguments to drm_memrange_init so we don't exceed our allocation.Eric Anholt
It takes (offset, size), not (offset, end).
2008-05-09GEM: Separate the LRU into execution list and LRU list.Eric Anholt
Now, the LRU list has objects that are completely done rendering and ready to kick out, while the execution list has things with active rendering, which have associated cookies and reference counts on them.
2008-05-09GEM: Clear obj_priv->agp_mem when we free it.Eric Anholt
Still managing to get something wrong with this, oopsing down in agp.
2008-05-09GEM: Avoid leaking refs on target objects on presumed offset success.Eric Anholt
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-12 07:05:30 +0000
{ enum { I830_INIT_DMA = 0x01, I830_CLEANUP_DMA = 0x02 } func; unsigned int mmio_offset; unsigned int buffers_offset; int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; unsigned int back_pitch; unsigned int depth_pitch; unsigned int cpp; } drm_i830_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i830_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i830_tex_region_t; typedef struct _drm_i830_sarea { unsigned int ContextState[I830_CTX_SETUP_SIZE]; unsigned int BufferState[I830_DEST_SETUP_SIZE]; unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; unsigned int Palette[2][256]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ int perf_boxes; /* performance boxes to be displayed */ /* Here's the state for texunits 2,3: */ unsigned int TexState2[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed2; unsigned int TexState3[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState3[I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed3; unsigned int StippleState[I830_STP_SETUP_SIZE]; } drm_i830_sarea_t; /* Flags for perf_boxes */ #define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ #define I830_BOX_FLIP 0x2 /* populated by kernel */ #define I830_BOX_WAIT 0x4 /* populated by kernel & client */ #define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ #define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ /* I830 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) #define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) #define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) #define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) #define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) #define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) #define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) #define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) #define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) #define DRM_IOCTL_I830_FLIP DRM_IO ( 0x49) #define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(0x4a, drm_i830_irq_emit_t) #define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( 0x4b, drm_i830_irq_wait_t) #define DRM_IOCTL_I830_GETPARAM DRM_IOWR(0x4c, drm_i830_getparam_t) #define DRM_IOCTL_I830_SETPARAM DRM_IOWR(0x4d, drm_i830_setparam_t) typedef struct _drm_i830_clear { int clear_color; int clear_depth; int flags; unsigned int clear_colormask; unsigned int clear_depthmask; } drm_i830_clear_t; /* These may be placeholders if we have more cliprects than * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i830_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i830_vertex_t; typedef struct _drm_i830_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void __user *address; /* Address to copy from */ } drm_i830_copy_t; typedef struct drm_i830_dma { void __user *virtual; int request_idx; int request_size; int granted; } drm_i830_dma_t; /* 1.3: Userspace can request & wait on irq's: */ typedef struct drm_i830_irq_emit { int __user *irq_seq; } drm_i830_irq_emit_t; typedef struct drm_i830_irq_wait { int irq_seq; } drm_i830_irq_wait_t; /* 1.3: New ioctl to query kernel params: */ #define I830_PARAM_IRQ_ACTIVE 1 typedef struct drm_i830_getparam { int param; int __user *value; } drm_i830_getparam_t; /* 1.3: New ioctl to set kernel params: */ #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 typedef struct drm_i830_setparam { int param; int value; } drm_i830_setparam_t; #endif /* _I830_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-12 07:05:29 +0000