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2007-10-17Bug #12838: Fix lock test client vs. server master race and misplaced closes.Robert Noland
2007-10-17Fix a race in the auth test where client prevents server from being master.Robert Noland
2007-10-17Bug #11870: FreeBSD hardware lock cleanup fix with multiple opens by a process.Jung-uk Kim
Previously, the lock would get released on the first close by the X Server (during AIGLX setup), and the Radeon driver would then hang in initialization due to unexpected failure in DRM calls that required the lock to be held. Based on a patch by Kostik Belousov.
2007-10-17Only allow creator to change shared buffer mask.Thomas Hellstrom
2007-10-17Remove the op ioctl, and replace it with a setuser ioctl.Thomas Hellstrom
Remove need for lock for now. May create races when we clean memory areas or on takedown. Needs to be fixed. Really do a validate on buffer creation in order to avoid problems with fixed memory buffers.
2007-10-17Revert "Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to ↵Thomas Hellstrom
set pinning." This reverts cf2d569daca6954d11a796f4d110148ae2e0c827 commit.
2007-10-17Revert "Copy the important parts of object_validate into object_create()."Thomas Hellstrom
This reverts f9c27aa50b715a7d21858f1ce9e4785120bd0c36 commit.
2007-10-17Revert "Remove the pinned buffer from the LRU when pinning."Thomas Hellstrom
This reverts 3a0bc518e35c62bb9c64c9105f836584d949653f commit.
2007-10-17Revert "Add some more verbosity to drm_bo_set_pin_req comments."Thomas Hellstrom
This reverts e7bfeb3031374653f7e55d67cc1b5c823849359f commit.
2007-10-17i915: lock struct mutex about buffer object lookupsDave Airlie
2007-10-16Revert part of earlier commit that caused an unresolved symbol for i915.Michel Dänzer
2007-10-16drm: drop drm bo list handling codeDave Airlie
2007-10-16drm: rename drmBOUnReference to drmBOUnreference for consistencyDave Airlie
2007-10-16Drop destroy ioctls for fences and buffer objects.Kristian Høgsberg
We now always create a drm_ref_object for user objects and this is then the only things that holds a reference to the user object. This way unreference on will destroy the user object when the last drm_ref_object goes way.
2007-10-16Take bo type argument out of the ioctl interface.Kristian Høgsberg
The buffer object type is still tracked internally, but it is no longer part of the user space visible ioctl interface. If the bo create ioctl specifies a non-NULL buffer address we assume drm_bo_type_user, otherwise drm_bo_type_dc. Kernel side allocations call drm_buffer_object_create() directly and can still specify drm_bo_type_kernel. Not 100% this makes sense either, but with this patch, the buffer type is no longer exported and we can clean up the internals later on.
2007-10-16Eliminate support for fake buffers.[utf-8] Kristian Høgsberg
2007-10-16nouveau: revert unintended change.Ben Skeggs
2007-10-16nouveau: Cleanup PGRAPH handler, attempt to survive PGRAPH exceptions.Ben Skeggs
2007-10-16nouveau: Survive PFIFO_CACHE_ERROR.Ben Skeggs
2007-10-16nouveau: Handle multiple PFIFO exceptions per irq, cleanup output.Ben Skeggs
2007-10-14nouveau: PPC fixes. These regs are very touchy.Stephane Marchesin
2007-10-14nouveau: fix warning.Jeremy Kolb
2007-10-14nouveau: fix warning.Jeremy Kolb
2007-10-14i915: fix vbl_swap allocationDave Airlie
2007-10-12nouveau: Fix a typo in nv25_graph_context_initPekka Paalanen
2007-10-12nouveau: Fix typos in nv20_graph_context_initStuart Bennett
2007-10-12nouveau: Make notifiers go into PCI memoryPekka Paalanen
On some hardware notifers in AGP memory just don't work.
2007-10-12nouveau: mandatory "oops I forgot half of the files" commitArthur Huillet
2007-10-12nouveau: added support for software methods, and implemented those necessary ↵Arthur Huillet
for NV04 (TNT1) to start X
2007-10-12i915: add superioctl support to i915Dave Airlie
This adds the initial i915 superioctl interface. The interface should be sufficent even if the implementation may needs fixes/optimisations internally in the drm wrt caching etc.
2007-10-12i915: check mask instead of flags for buffer fence typesDave Airlie
2007-10-10FreeBSD: Fill in domain field when supported.Eric Anholt
2007-10-10Eliminate trailing whitespace from last commit.Ian Romanick
2007-10-10Fix command list submission on big-endian.Ian Romanick
2007-10-10nouveau : nv10 and nv04 PGRAPH_NSTATUS are differentMatthieu Castet
2007-10-10nouveau: PMC_BOOT_1 was not mapped.Maarten Maathuis
2007-10-10Only add native-type on EXE signals. Otherwise flush flags mayThomas Hellstrom
get out of sync.
2007-10-10nouveau: try to fix big endian.Stephane Marchesin
2007-10-07nouveau: A char is signed, so it may overflow for >NV50.Maarten Maathuis
2007-10-06nouveau : print correct value in nouveau_graph_dump_trap_info for nv04Matthieu Castet
2007-10-05Merge branch 'pre-superioctl-branch'Dave Airlie
2007-10-04nouveau: Remove excess device classes.Maarten Maathuis
2007-10-04nouveau: NV47 context switching voodoo + warningMaarten Maathuis
2007-10-04nouveau: Switch over to using PMC_BOOT_0 for card detection.Maarten Maathuis
2007-10-04linux-drm: Obey device class requirements when detecting devices.Maarten Maathuis
2007-10-04drm: fix page count calculationDave Airlie
Also no need to do pre-populate work on single page
2007-10-04nouveau: nv2a drm context switch support.Stephane Marchesin
2007-10-03Use 'ifdef __BIG_ENDIAN' instead of 'if __BIG_ENDIAN'Ian Romanick
2007-10-03First round of byte-ordering fixes for PowerPC.Ian Romanick
This isn't 100% as command submission via PCI-e GART buffers doesn't work. I've hacked around that for the time being. This is essentially the code that was used at the POWER.org event to show Bimini.
2007-10-02nouveau: nv20 graph_create_context differencePekka Paalanen
nv20 writes the chan->id to a different place than nv28. This still does not make nv20 run nv10_demo.
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 13:23:23 +0000
buffers_offset; #endif int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; } drm_i810_pre12_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i810_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i810_tex_region_t; typedef struct _drm_i810_sarea { unsigned int ContextState[I810_CTX_SETUP_SIZE]; unsigned int BufferState[I810_DEST_SETUP_SIZE]; unsigned int TexState[2][I810_TEX_SETUP_SIZE]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ } drm_i810_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ /* i810 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_I810_INIT 0x00 #define DRM_I810_VERTEX 0x01 #define DRM_I810_CLEAR 0x02 #define DRM_I810_FLUSH 0x03 #define DRM_I810_GETAGE 0x04 #define DRM_I810_GETBUF 0x05 #define DRM_I810_SWAP 0x06 #define DRM_I810_COPY 0x07 #define DRM_I810_DOCOPY 0x08 #define DRM_I810_OV0INFO 0x09 #define DRM_I810_FSTATUS 0x0a #define DRM_I810_OV0FLIP 0x0b #define DRM_I810_MC 0x0c #define DRM_I810_RSTATUS 0x0d #define DRM_I810_FLIP 0x0e #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i810_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i810_vertex_t; typedef struct _drm_i810_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i810_copy_t; #define PR_TRIANGLES (0x0<<18) #define PR_TRISTRIP_0 (0x1<<18) #define PR_TRISTRIP_1 (0x2<<18) #define PR_TRIFAN (0x3<<18) #define PR_POLYGON (0x4<<18) #define PR_LINES (0x5<<18) #define PR_LINESTRIP (0x6<<18) #define PR_RECTS (0x7<<18) #define PR_MASK (0x7<<18) typedef struct drm_i810_dma { void *virtual; int request_idx; int request_size; int granted; } drm_i810_dma_t; typedef struct _drm_i810_overlay_t { unsigned int offset; /* Address of the Overlay Regs */ unsigned int physical; } drm_i810_overlay_t; typedef struct _drm_i810_mc { int idx; /* buffer index */ int used; /* nr bytes in use */ int num_blocks; /* number of GFXBlocks */ int *length; /* List of lengths for GFXBlocks (FUTURE) */ unsigned int last_render; /* Last Render Request */ } drm_i810_mc_t; #endif /* _I810_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 13:23:23 +0000