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2010-03-07intel: Repeat execbuffer if interrupted by signalChris Wilson
Repeat while EINTR, not EAGAIN! One more source of corruption erradicated, hurray! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-03-06nouveau: Update nouveau_class.h.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2010-03-04intel: Only align Y-tiling pitch to the Y tile width.Eric Anholt
Fixes piglit depth-tex-modes on gen4.
2010-03-04intel: Propagate some more error returnsChris Wilson
Ensure that errors from the kernel are propagated back to the caller, and not masked with return 0; Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-03-03Increment version to 2.4.19 for release.Eric Anholt
The primary motivation of this release is to expose the new execbuf2 Intel API.
2010-03-03intel: Update the needs_fence flag of buffers on the validate list.Eric Anholt
Fixes fbo-copyteximage on i915 with texture tiling and execbuf2 fenced relocs.
2010-03-02intel: Don't enable execbuf2 fenced relocs unless we have execbuf2.Eric Anholt
2010-03-02intel: Don't tile-align pitch for untiled buffers.Eric Anholt
This allows Mesa to use drm_intel_bo_alloc_tiled() for its tiled buffers, since it makes its decision about pitch before telling libdrm. They happen to be the same choices for the tiled case.
2010-03-02intel: Fix typo in conversion from IS_GEN to bufmgr_gem->gen.Eric Anholt
Luckily I caught the bug with the first consumer of the interface.
2010-03-02intel: add a comment about tiled buffer alloc height alignment from Mesa.Eric Anholt
2010-03-02nouveau: make sure initial kalloc for user bo ends up in the right placeMaarten Maathuis
- Currently reloc'ing a user bo to gart will first cause an allocation in vram, which is then written to by cpu, then the bo gets moved to gart. Acked-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
2010-03-02intel: Use an integer for chipset generation instead of many conditionals.Eric Anholt
Saves a bunch of comparisons in hot paths.
2010-03-02libdrm/intel: execbuf2 supportJesse Barnes
This patch to libdrm adds support for the new execbuf2 ioctl. If detected, it will be used instead of the old ioctl. By using the new drm_intel_bufmgr_gem_enable_fenced_relocs(), you can indicate that any time a fence register is actually required for a relocation target you will call drm_intel_bo_emit_reloc_fence instead of drm_intel_bo_emit_reloc, which will reduce fence register pressure. Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-28tests/modetest: Don't get_props on a connector after freeing it.Marcin Kościelnicki
2010-02-28tests: vrefresh is actually not * 1000.Marcin Kościelnicki
2010-02-28tests: Add nouveau to list of supported modules.Marcin Kościelnicki
2010-02-28libkms/nouveau: Add supportMarcin Kościelnicki
2010-02-28libkms/intel: Throw out unused intel_bo fields.Marcin Kościelnicki
Acked-by: Jakob Bornecrantz <jakob@vmware.com>
2010-02-28Add config.h macro HAVE_NOUVEAUMarcin Kościelnicki
2010-02-25intel: Add initial support for Sandybridge, and clean up the #defines.Eric Anholt
2010-02-25nouveau: Update nouveau_class.h.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2010-02-20nv30: update for 8 texture unitsPatrice Mandin
2010-02-20nv30: update for front/back stencil inversionPatrice Mandin
Signed-off-by: Patrice Mandin <patmandin@gmail.com>
2010-02-18libkms: Use a standard version numberJakob Bornecrantz
2010-02-18libkms: Enable by defaultJakob Bornecrantz
2010-02-18libkms: Add missing include file to libkms sourceJakob Bornecrantz
2010-02-18vmwgfx: Update kernel headerJakob Bornecrantz
2010-02-18radeon: add square-tiling flagMarek Olšák
2010-02-16Increment version to 2.4.18 for release.Carl Worth
The primary motivation of the release is the bug fix in commit 4f0f871730b76730ca58209181d16725b0c40184
2010-02-16nouveau: bump MAX_PUSH to 512Ben Skeggs
2010-02-16nouveau: interface changes for 0.0.16 DRMLuca Barbieri
This commit encompasses the changes necessary to run on top of the 0.0.16 nouveau interface, additional APIs to support the new features of the interface, as well as code from Luca Barbieri to improve the pushbuf interface, which just happens to break nouveau's libdrm ABI so was delayed until now. API changes as a result of 0.0.16 DRM interface: 1. No more bo_pin()/bo_unpin(), these were only there for UMS and we no longer support it. 2. Any random nouveau_bo can be submitted to the GPU as a push buffer. 3. Relocations can be applied on any nouveau_bo This patch changes the pushbuffer ABI to: 1. No longer use/expose nouveau_pushbuffer. Everything is directly in nouveau_channel. This saves the extra "pushbuf" pointer dereference. 2. Use cur/end pointers instead of tracking the remaining size. Pushing data now only needs to alter cur and not both cur and remaining. The goal is to make the *_RING macros faster and make the interface simpler and cleaner in the process. The *_RING APIs are unchanged, but those are inlined and the ABI is changed. Also, anything accessing pushbuf->remaining instead of using AVAIL_RING will need to be fixed.
2010-02-10drm: a some new connector types from the kernelAlex Deucher
Add eDP (embedded displayport) and generic TV Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-02-10intel: Handle resetting of input params after EINTR during SET_TILINGChris Wilson
The SET_TILING is pernicious in that it overwrites the input arguments following an error in order to report the current tiling state of the buffer. This caught us by surprise as we then fed those arguments back into to the ioctl unmodified following an EINTR and so the kernel then reported success for the no-op. We interpreted this success as meaning that the tiling on the buffer had changed so updated our state and started using the buffer incorrectly in the new tiled/untiled manner. This lead to all sorts of random corruption and GPU hangs, even though the batch buffers would look sane (when the GPU had not wandered off into forbidden territory). References: Bug 25475 - [i915] Xorg crash / Execbuf while wedged http://bugs.freedesktop.org/show_bug.cgi?id=25475 Bug 25554 - i830_uxa_prepare_access: gtt bo map failed: Input/output error http://bugs.freedesktop.org/show_bug.cgi?id=25554 (And probably every other weird bug in the last few months.) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-09intel: Account for potential pinned buffers hogging fencesChris Wilson
As the kernel reports the total number of fences, we must guess how many fences are likely to be pinned. In the typical system these will be only used by the scanout buffers, of which there may be one per pipe, and any number of manually pinned fenced buffers. So take a conservative guess and reserve two fences for use by the system. Note this reduces the number of fences to 3 for i915 and prior. Reference: http://bugs.freedesktop.org/show_bug.cgi?id=25911 The latest intel driver 2.10.0 causes kernel oops and system hangs Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-04Tidy up compile warnings by cleaning up types.Matthew W. S. Bell
2010-02-04libdrm/radeon: Fix section size mismatch to reset the section.Pauli Nieminen
If there is section size mismatch reusing the section object makes section start fail. Reseting the object before doing error checking prevents the possible flood of errors.
2010-02-02radeon: enable by default now that kms is out of stagingDave Airlie
2010-02-02intel: check return value for callocDave Airlie
2010-02-01nouveau: Regenerate nouveau_class.h.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2010-01-31nouveau: add nouveau_resource_destroyMarcin Slusarz
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2010-01-28libkms: Rework interface to not duplicate fields from kms and make formats ↵Jakob Bornecrantz
explicit List of changes: Fixes the cursor size to 64x64, you still need ti supply width and height Explicitly make the cursor format A8R8G8B8 Explicitly make the scanout format X8R8G8B8
2010-01-27nouveau: Update nouveau_drm.hMarcin Kościelnicki
2010-01-23libkms: Fix return value in vmwgfx_bo_createJakob Bornecrantz
2010-01-21nouveau: fail channel creation if pushbuf init failsBen Skeggs
2010-01-20intel: Add pkg-config dependency on libdrm.so using 'Requires'Chris Wilson
2010-01-16Support gcc's __FUNCTION__ for people using other compilersAlan Coopersmith
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
2010-01-16Add support for Solaris libc atomic operationsAlan Coopersmith
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
2010-01-16Include alloca.h in tests/drmstat.c when configure detects itAlan Coopersmith
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
2010-01-15nouveau: disable flush_notify on channel_freeMarcin Slusarz
We don't want do call flush_notify when we will FIRE the RING a couple of lines later, because grobj bound to this channel might be already freed.
2010-01-15nouveau: fix memory leak in nouveau_channel_freeMarcin Slusarz
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-24 20:04:57 +0000
cal_map_t *cce_ring; drm_local_map_t *ring_rptr; drm_local_map_t *buffers; drm_local_map_t *agp_textures; } drm_r128_private_t; typedef struct drm_r128_buf_priv { u32 age; int prim; int discard; int dispatched; drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; /* r128_cce.c */ extern int r128_cce_init( DRM_IOCTL_ARGS ); extern int r128_cce_start( DRM_IOCTL_ARGS ); extern int r128_cce_stop( DRM_IOCTL_ARGS ); extern int r128_cce_reset( DRM_IOCTL_ARGS ); extern int r128_cce_idle( DRM_IOCTL_ARGS ); extern int r128_engine_reset( DRM_IOCTL_ARGS ); extern int r128_fullscreen( DRM_IOCTL_ARGS ); extern int r128_cce_buffers( DRM_IOCTL_ARGS ); extern int r128_getparam( DRM_IOCTL_ARGS ); extern void r128_freelist_reset( drm_device_t *dev ); extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); extern int r128_do_cleanup_cce( drm_device_t *dev ); extern int r128_do_cleanup_pageflip( drm_device_t *dev ); /* r128_state.c */ extern int r128_cce_clear( DRM_IOCTL_ARGS ); extern int r128_cce_swap( DRM_IOCTL_ARGS ); extern int r128_cce_flip( DRM_IOCTL_ARGS ); extern int r128_cce_vertex( DRM_IOCTL_ARGS ); extern int r128_cce_indices( DRM_IOCTL_ARGS ); extern int r128_cce_blit( DRM_IOCTL_ARGS ); extern int r128_cce_depth( DRM_IOCTL_ARGS ); extern int r128_cce_stipple( DRM_IOCTL_ARGS ); extern int r128_cce_indirect( DRM_IOCTL_ARGS ); /* Register definitions, register access macros and drmAddMap constants * for Rage 128 kernel driver. */ #define R128_AUX_SC_CNTL 0x1660 # define R128_AUX1_SC_EN (1 << 0) # define R128_AUX1_SC_MODE_OR (0 << 1) # define R128_AUX1_SC_MODE_NAND (1 << 1) # define R128_AUX2_SC_EN (1 << 2) # define R128_AUX2_SC_MODE_OR (0 << 3) # define R128_AUX2_SC_MODE_NAND (1 << 3) # define R128_AUX3_SC_EN (1 << 4) # define R128_AUX3_SC_MODE_OR (0 << 5) # define R128_AUX3_SC_MODE_NAND (1 << 5) #define R128_AUX1_SC_LEFT 0x1664 #define R128_AUX1_SC_RIGHT 0x1668 #define R128_AUX1_SC_TOP 0x166c #define R128_AUX1_SC_BOTTOM 0x1670 #define R128_AUX2_SC_LEFT 0x1674 #define R128_AUX2_SC_RIGHT 0x1678 #define R128_AUX2_SC_TOP 0x167c #define R128_AUX2_SC_BOTTOM 0x1680 #define R128_AUX3_SC_LEFT 0x1684 #define R128_AUX3_SC_RIGHT 0x1688 #define R128_AUX3_SC_TOP 0x168c #define R128_AUX3_SC_BOTTOM 0x1690 #define R128_BRUSH_DATA0 0x1480 #define R128_BUS_CNTL 0x0030 # define R128_BUS_MASTER_DIS (1 << 6) #define R128_CLOCK_CNTL_INDEX 0x0008 #define R128_CLOCK_CNTL_DATA 0x000c # define R128_PLL_WR_EN (1 << 7) #define R128_CONSTANT_COLOR_C 0x1d34 #define R128_CRTC_OFFSET 0x0224 #define R128_CRTC_OFFSET_CNTL 0x0228 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) #define R128_DP_GUI_MASTER_CNTL 0x146c # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) # define R128_GMC_BRUSH_NONE (15 << 4) # define R128_GMC_DST_16BPP (4 << 8) # define R128_GMC_DST_24BPP (5 << 8) # define R128_GMC_DST_32BPP (6 << 8) # define R128_GMC_DST_DATATYPE_SHIFT 8 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define R128_GMC_AUX_CLIP_DIS (1 << 29) # define R128_GMC_WR_MSK_DIS (1 << 30) # define R128_ROP3_S 0x00cc0000 # define R128_ROP3_P 0x00f00000 #define R128_DP_WRITE_MASK 0x16cc #define R128_DST_PITCH_OFFSET_C 0x1c80 # define R128_DST_TILE (1 << 31) #define R128_GEN_INT_CNTL 0x0040 # define R128_CRTC_VBLANK_INT_EN (1 << 0) #define R128_GEN_INT_STATUS 0x0044 # define R128_CRTC_VBLANK_INT (1 << 0) # define R128_CRTC_VBLANK_INT_AK (1 << 0) #define R128_GEN_RESET_CNTL 0x00f0 # define R128_SOFT_RESET_GUI (1 << 0) #define R128_GUI_SCRATCH_REG0 0x15e0 #define R128_GUI_SCRATCH_REG1 0x15e4 #define R128_GUI_SCRATCH_REG2 0x15e8 #define R128_GUI_SCRATCH_REG3 0x15ec #define R128_GUI_SCRATCH_REG4 0x15f0 #define R128_GUI_SCRATCH_REG5 0x15f4 #define R128_GUI_STAT 0x1740 # define R128_GUI_FIFOCNT_MASK 0x0fff # define R128_GUI_ACTIVE (1 << 31) #define R128_MCLK_CNTL 0x000f # define R128_FORCE_GCP (1 << 16) # define R128_FORCE_PIPE3D_CP (1 << 17) # define R128_FORCE_RCP (1 << 18) #define R128_PC_GUI_CTLSTAT 0x1748 #define R128_PC_NGUI_CTLSTAT 0x0184 # define R128_PC_FLUSH_GUI (3 << 0) # define R128_PC_RI_GUI (1 << 2) # define R128_PC_FLUSH_ALL 0x00ff # define R128_PC_BUSY (1 << 31) #define R128_PCI_GART_PAGE 0x017c #define R128_PRIM_TEX_CNTL_C 0x1cb0 #define R128_SCALE_3D_CNTL 0x1a00 #define R128_SEC_TEX_CNTL_C 0x1d00 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c #define R128_SETUP_CNTL 0x1bc4 #define R128_STEN_REF_MASK_C 0x1d40 #define R128_TEX_CNTL_C 0x1c9c # define R128_TEX_CACHE_FLUSH (1 << 23) #define R128_WAIT_UNTIL 0x1720 # define R128_EVENT_CRTC_OFFSET (1 << 0) #define R128_WINDOW_XY_OFFSET 0x1bcc /* CCE registers */ #define R128_PM4_BUFFER_OFFSET 0x0700 #define R128_PM4_BUFFER_CNTL 0x0704 # define R128_PM4_MASK (15 << 28) # define R128_PM4_NONPM4 (0 << 28) # define R128_PM4_192PIO (1 << 28) # define R128_PM4_192BM (2 << 28) # define R128_PM4_128PIO_64INDBM (3 << 28) # define R128_PM4_128BM_64INDBM (4 << 28) # define R128_PM4_64PIO_128INDBM (5 << 28) # define R128_PM4_64BM_128INDBM (6 << 28) # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) #define R128_PM4_BUFFER_WM_CNTL 0x0708 # define R128_WMA_SHIFT 0 # define R128_WMB_SHIFT 8 # define R128_WMC_SHIFT 16 # define R128_WB_WM_SHIFT 24 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c #define R128_PM4_BUFFER_DL_RPTR 0x0710 #define R128_PM4_BUFFER_DL_WPTR 0x0714 # define R128_PM4_BUFFER_DL_DONE (1 << 31) #define R128_PM4_VC_FPU_SETUP 0x071c #define R128_PM4_IW_INDOFF 0x0738 #define R128_PM4_IW_INDSIZE 0x073c #define R128_PM4_STAT 0x07b8 # define R128_PM4_FIFOCNT_MASK 0x0fff # define R128_PM4_BUSY (1 << 16) # define R128_PM4_GUI_ACTIVE (1 << 31) #define R128_PM4_MICROCODE_ADDR 0x07d4 #define R128_PM4_MICROCODE_RADDR 0x07d8 #define R128_PM4_MICROCODE_DATAH 0x07dc #define R128_PM4_MICROCODE_DATAL 0x07e0 #define R128_PM4_BUFFER_ADDR 0x07f0 #define R128_PM4_MICRO_CNTL 0x07fc # define R128_PM4_MICRO_FREERUN (1 << 30) #define R128_PM4_FIFO_DATA_EVEN 0x1000 #define R128_PM4_FIFO_DATA_ODD 0x1004 /* CCE command packets */ #define R128_CCE_PACKET0 0x00000000 #define R128_CCE_PACKET1 0x40000000 #define R128_CCE_PACKET2 0x80000000 #define R128_CCE_PACKET3 0xC0000000 # define R128_CNTL_HOSTDATA_BLT 0x00009400 # define R128_CNTL_PAINT_MULTI 0x00009A00 # define R128_CNTL_BITBLT_MULTI 0x00009B00 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 #define R128_CCE_PACKET_MASK 0xC0000000 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 #define R128_CCE_PACKET0_REG_MASK 0x000007ff #define R128_CCE_PACKET1_REG0_MASK 0x000007ff #define R128_CCE_PACKET1_REG1_MASK 0x003ff800 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 #define R128_CCE_VC_CNTL_NUM_SHIFT 16 #define R128_DATATYPE_VQ 0 #define R128_DATATYPE_CI4 1 #define R128_DATATYPE_CI8 2 #define R128_DATATYPE_ARGB1555 3 #define R128_DATATYPE_RGB565 4 #define R128_DATATYPE_RGB888 5 #define R128_DATATYPE_ARGB8888 6 #define R128_DATATYPE_RGB332 7 #define R128_DATATYPE_Y8 8 #define R128_DATATYPE_RGB8 9 #define R128_DATATYPE_CI16 10 #define R128_DATATYPE_YVYU422 11 #define R128_DATATYPE_VYUY422 12 #define R128_DATATYPE_AYUV444 14 #define R128_DATATYPE_ARGB4444 15 /* Constants */ #define R128_AGP_OFFSET 0x02000000 #define R128_WATERMARK_L 16 #define R128_WATERMARK_M 8 #define R128_WATERMARK_N 8 #define R128_WATERMARK_K 128 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 #define R128_MAX_VB_AGE 0x7fffffff #define R128_MAX_VB_VERTS (0xffff) #define R128_RING_HIGH_MARK 128 #define R128_PERFORMANCE_BOXES 0 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define R128_WRITE_PLL(addr,val) \ do { \ R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ ((addr) & 0x1f) | R128_PLL_WR_EN); \ R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ } while (0) extern int R128_READ_PLL(drm_device_t *dev, int addr); #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ ((n) << 16) | ((reg) >> 2)) #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ (((reg1) >> 2) << 11) | ((reg0) >> 2)) #define CCE_PACKET2() (R128_CCE_PACKET2) #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ (pkt) | ((n) << 16)) static __inline__ void r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); if ( ring->space <= 0 ) ring->space += ring->size; } /* ================================================================ * Misc helper macros */ #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ if ( ring->space < ring->high_mark ) { \ for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ r128_update_ring_snapshot( dev_priv ); \ if ( ring->space >= ring->high_mark ) \ goto __ring_space_done; \ DRM_UDELAY(1); \ } \