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2007-09-06Bump version to 1.0.0.Ian Romanick
2007-09-06nouveau: fix some nv04 graph switching.Stephane Marchesin
2007-09-06nouveau: add pure nv30 support.Stephane Marchesin
2007-09-04Add context init voodoo and context switch code for NV41.Maarten Maathuis
2007-08-31Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into ↵Ian Romanick
xgi-0-0-2
2007-08-31Acutally emit the IRQ (duh) when setting the fence post.Ian Romanick
2007-08-31nouveau: nv04 context switching support. Works for starting X up at least.Stephane Marchesin
2007-08-31nouveau: give nv03 the last cut.Stephane Marchesin
2007-08-29Use ati_pcigart for PCI-e GART table handling.Ian Romanick
2007-08-29Fix late night dumb-dumb mistake.Ian Romanick
2007-08-29Use DRM_SPINLOCK / DRM_UNSPINLOCK macros.Ian Romanick
2007-08-28Add register defines for hw binningKeith Packard
2007-08-28drm: remove XFREE86_VERSION macrosDave Airlie
2007-08-26nouveau : add NV04_PGRAPH_TRAPPED_ADDR definitionMatthieu Castet
- fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-25nouveau : nv1x graph reworksMatthieu Castet
- add forgotten init value - use the same PGRAPH_DEBUG than the blob - remove init of ddx reg : it should be done with object - better handle of channel destruction hope I didn't break anything ;)
2007-08-25nouveau: nv10: output a warning if last channel invalid, and switch to nextPatrice Mandin
2007-08-23nouveau: nv10: check some NULL pointers inside context switchPatrice Mandin
2007-08-22nouveau : fix some potential crashes with objects causing hash collisionMatthieu Castet
2007-08-22nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do.Ben Skeggs
2007-08-22nouveau/nv40: Dump extra info on ucode state if ctx switch fails.Ben Skeggs
2007-08-22nouveau: NV4c ctx ucode.Ben Skeggs
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the ucode matches it still.
2007-08-22nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.Ben Skeggs
2007-08-22nouveau: redo nv30_graph.c. Should work better, but we still lack a couple ↵Stephane Marchesin
of cards.
2007-08-22nouveau: fix the comment and debug message for PCIGART sizeStephane Marchesin
2007-08-21nouveau: Add NV44 ctx ucode. Patch from stillunknown.Ben Skeggs
Microcode is similar enough to the NV4A one that it should be able to use the same initial PGRAPH context. One day this mess will go away, honest..
2007-08-21nouveau: Poke 0x2230 on NV47 also.Ben Skeggs
Makes 0x2220 work the same way as on NV40.
2007-08-19Check also for Linux, as it's not supported on different OSPatrice Mandin
2007-08-19Function pci_get_bus_and_slot needs 2.6.19 or laterPatrice Mandin
2007-08-17Remove unnecessary include.Ian Romanick
2007-08-16Forgot to add this file on the last commit.Ian Romanick
2007-08-16Merge branch 'master' into bo-set-pinEric Anholt
2007-08-17nouveau: Detect memory on NFORCE/NFORCE2 correctly.Ben Skeggs
2007-08-15Implement fence support.Ian Romanick
2007-08-15Fix dev->agp->base initialization on BSD, and fix addmap range check on Linux.Eric Anholt
With the previous linux commit, an AGP aperture at the end of the address space would have wrapped to 0 and the test would have failed.
2007-08-15BSD: Return EINVAL if drm_unlock is called on an unheld or other-owner lock.Eric Anholt
2007-08-15Add a set of tests for DRM locking, exposing issues on BSD.Eric Anholt
2007-08-15Fix a bad error message in auth.c regression test.Eric Anholt
2007-08-15Require master in setversion test, since it requires auth.Eric Anholt
2007-08-15BSD: simplify drm_ioctl() after other refactoring.vehemens
2007-08-15Bug #11989: Fix regression in getstats ioctl (kernel panic).vehemens
2007-08-15BSD: Fix regression in setversion ioctl (current version not returned).Eric Anholt
2007-08-15Add a regression test for the setversion interface.Eric Anholt
2007-08-15Add simple regression test for getstats (does it not crash the kernel?).Eric Anholt
2007-08-15BSD: Replace brief description in each file's first line with doxygen later on.Eric Anholt
The brief descriptions usually had the wrong filename in them.
2007-08-15nouveau: Use count parameter in nouveau_notifier_alloc().Ben Skeggs
2007-08-15nouveau: Turn some messages into DRM_DEBUGs..Ben Skeggs
2007-08-15nouveau: Allow GART notifiers when using sgdma code.Ben Skeggs
2007-08-15nouveau: Workaround mysterious PRAMIN clobbering by the card.Ben Skeggs
2007-08-14Eliminate unused / useless ioctls.Ian Romanick
2007-08-14Clean up remaining C++ style comments.Ian Romanick
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 13:00:59 +0000
hl ppc">#define MGA_LOG_MIN_TEX_REGION_SIZE 16 #endif /* __MGA_SAREA_DEFINES__ */ /* Setup registers for 3D context */ typedef struct { unsigned int dstorg; unsigned int maccess; unsigned int plnwt; unsigned int dwgctl; unsigned int alphactrl; unsigned int fogcolor; unsigned int wflag; unsigned int tdualstage0; unsigned int tdualstage1; unsigned int fcol; unsigned int stencil; unsigned int stencilctl; } drm_mga_context_regs_t; /* Setup registers for 2D, X server */ typedef struct { unsigned int pitch; } drm_mga_server_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int texctl; unsigned int texctl2; unsigned int texfilter; unsigned int texbordercol; unsigned int texorg; unsigned int texwidth; unsigned int texheight; unsigned int texorg1; unsigned int texorg2; unsigned int texorg3; unsigned int texorg4; } drm_mga_texture_regs_t; /* General aging mechanism */ typedef struct { unsigned int head; /* Position of head pointer */ unsigned int wrap; /* Primary DMA wrap count */ } drm_mga_age_t; typedef struct _drm_mga_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ drm_mga_context_regs_t context_state; drm_mga_server_regs_t server_state; drm_mga_texture_regs_t tex_state[2]; unsigned int warp_pipe; unsigned int dirty; unsigned int vertsize; /* The current cliprects, or a subset thereof. */ drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Information about the most recently used 3d drawable. The * client fills in the req_* fields, the server fills in the * exported_ fields and puts the cliprects into boxes, above. * * The client clears the exported_drawable field before * clobbering the boxes data. */ unsigned int req_drawable; /* the X drawable id */ unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ unsigned int exported_drawable; unsigned int exported_index; unsigned int exported_stamp; unsigned int exported_buffers; unsigned int exported_nfront; unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ unsigned int status[4]; unsigned int last_wrap; drm_mga_age_t last_frame; unsigned int last_enqueue; /* last time a buffer was enqueued */ unsigned int last_dispatch; /* age of the most recently dispatched buffer */ unsigned int last_quiescent; /* */ /* LRU lists for texture memory in agp space and on the card. */ drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; unsigned int texAge[MGA_NR_TEX_HEAPS]; /* Mechanism to validate card state. */ int ctxOwner; } drm_mga_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ /* MGA specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) #define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) #define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) #define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(0x49, drm_mga_getparam_t) typedef struct _drm_mga_warp_index { int installed; unsigned long phys_addr; int size; } drm_mga_warp_index_t; typedef struct drm_mga_init { enum { MGA_INIT_DMA = 0x01, MGA_CLEANUP_DMA = 0x02 } func; unsigned long sarea_priv_offset; int chipset; int sgram; unsigned int maccess; unsigned int fb_cpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_cpp; unsigned int depth_offset, depth_pitch; unsigned int texture_offset[MGA_NR_TEX_HEAPS]; unsigned int texture_size[MGA_NR_TEX_HEAPS]; unsigned long fb_offset; unsigned long mmio_offset; unsigned long status_offset; unsigned long warp_offset; unsigned long primary_offset; unsigned long buffers_offset; } drm_mga_init_t; typedef struct drm_mga_fullscreen { enum { MGA_INIT_FULLSCREEN = 0x01, MGA_CLEANUP_FULLSCREEN = 0x02 } func; } drm_mga_fullscreen_t; typedef struct drm_mga_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; } drm_mga_clear_t; typedef struct drm_mga_vertex { int idx; /* buffer to queue */ int used; /* bytes in use */ int discard; /* client finished with buffer? */ } drm_mga_vertex_t; typedef struct drm_mga_indices { int idx; /* buffer to queue */ unsigned int start; unsigned int end; int discard; /* client finished with buffer? */ } drm_mga_indices_t; typedef struct drm_mga_iload { int idx; unsigned int dstorg; unsigned int length; } drm_mga_iload_t; typedef struct _drm_mga_blit { unsigned int planemask; unsigned int srcorg; unsigned int dstorg; int src_pitch, dst_pitch; int delta_sx, delta_sy; int delta_dx, delta_dy; int height, ydir; /* flip image vertically */ int source_pitch, dest_pitch; } drm_mga_blit_t; /* 3.1: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define MGA_PARAM_IRQ_NR 1 typedef struct drm_mga_getparam { int param; int *value; } drm_mga_getparam_t; #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 13:00:59 +0000