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2009-02-23Add libdrm_intel.pc by popular demand.Eric Anholt
2009-02-23Fix DRM_CAS() on Alpha. (#16549)Ivan Kokshaysky
2009-02-23modetest: Print names of properties.Kristian Høgsberg
2009-02-22Fix fix distcheck for optional nouveau stuff.Pekka Paalanen
Tylo. Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-02-21Fix distcheck for optional nouveau stuff.Eric Anholt
2009-02-21Bump version to 2.4.5 for new API additions.Eric Anholt
2009-02-21intel: Add a new bufmgr alloc function to get BOs ready for rendering to.Eric Anholt
This avoids using the oldest BO in the BO cache and waiting for it to be idle before we turn around and render to it with the GPU. Thanks to Chris Wilson for pointing out how silly we were being.
2009-02-20libdrm/nouveau: free drmVersion after we're done with itBen Skeggs
2009-02-20libdrm/nouveau: fix dma debuggingBen Skeggs
2009-02-18nouveau: support backlight only when kernel doesPekka Paalanen
Loading nouveau.ko would fail with unknown symbols, if the backlight class device support is not provided in the kernel. Let's make the backlight support dependant on the kernel configuration. This is a bit ugly, the proper way would be to check for the config in Makefile.kernel whether to build nouveau_backlight.o at all, and if not, nouveau_drv.h should provide the stubs. Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-02-18nv40, nv50: fix backlight build for <2.6.29 kernelsMatthew Garrett
Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-02-18nouveau: Add in-kernel backlight control supportMatthew Garrett
Several nvidia-based systems don't support backlight control via the standard ACPI control mechanisms. Instead, it's necessary for the driver to modify the backlight control registers directly. This patch adds support for determining whether the registers appear to be in use, and if so registers a kernel backlight device to control them. The backlight can then be controlled via existing userspace tools. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2009-02-16drm_compat: remove kmap_atomic_prot_pfn()Pekka Paalanen
This function is unused, and yet creates build problems: the symbol init_mm is not exported by the latest -rc kernels and I don't believe it ever will be. Even CONFIG_UNUSED_SYMBOLS does not provide it anymore. If this function is needed in the future, it needs to be reinvented in any case. So remove it. Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-02-16Remove i915 driver sources from linux-corePekka Paalanen
Intel developers have stated, that their DRM development continues elsewhere in some Linux kernel trees. This makes the code in drm.git just dead weight. This removal allows further cleanup of compatibility code. shared-core and bsd-core are left untouched this time. Signed-off-by: Pekka Paalanen <pq@iki.fi> Acked-by: Eric Anholt <eric@anholt.net>
2009-02-15intel: Clear ioctl parameter outvalues and pads that confuse valgrind.Eric Anholt
The minor CPU cost here is probably outweighed by bothering us with noise in the tool.
2009-02-15nv40: fail completely if we don't have a ctxprog for the chipsetBen Skeggs
2009-02-15nv50: context info for chipset 0xa0Ben Skeggs
2009-02-15libdrm: make libdrm_nouveau conditional, disabled by defaultBen Skeggs
libdrm isn't supposed to ship APIs not present in a released kernel.
2009-02-11mode: Make xfdrmMode.[c|h] not depend on drm_mode.hJakob Bornecrantz
2009-02-11nouveau: fix type warnings: void* arith, un/signedPekka Paalanen
nouveau_notifier.c had two places where void* was used in arithmetic, fixed by using char*. nouveau_dma_wait(), nouveau_notifier_wait_status() and nouveau_resource_alloc() had signed/unsigned comparison warnings, fixed by changing the function parameter into an unsigned type. Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-02-11drm/nv50: fix nv9x chipsetsBen Skeggs
NVIDIA do this fun little sequence after updating the PRAMIN page tables. On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one) worked, hence the majority of the setup needed to create a channel ended up in the wrong place, causing all sorts of fun. This is done by NVIDIA on nv8x chips also, so we'll do it for them too, even though they appear to work without it.
2009-02-11drm/nv50: add context info for nv98Ben Skeggs
It won't work yet, just like the other 9xxx chips. Real soon now :)
2009-02-10drm/nv50: use a slightly different initial context for nv96Ben Skeggs
I'm not 100% sure that the nv94 one we were using won't work. The context layouts are identical (well.. same ctxprog, so of course!), only a couple of registers differ. But, be safe until we actually get some 9xxx chips working.
2009-02-10drm/nv50: correct ramfc pointer in channel headerBen Skeggs
Suprisingly the card still worked without this...
2009-02-10drm/nv50: let the card handle the initial context switchBen Skeggs
Our PFIFO/PGRAPH context save/load functions don't really work well (at all?) on nv5x yet. Depending on what random state the card is in before the drm loads, fbcon probably won't work correctly. Luckily we've setup the GPU in such a way that it'll actually do a hw context switch for the first context. Not sure of how successful this'd be currently on the older chips (actually, pretty sure it won't work), so NV50 only for now.
2009-02-07nouveau: don't try to traverse non-existent listsStuart Bennett
Fixes nouveau_ioctl_mem_free Oops
2009-02-05nouveau: fix some issues where buffer objects never get freedBen Skeggs
2009-02-04modetest: Add syntax to also specify a crtc when setting a mode.Kristian Høgsberg
2009-02-04nouveau: install libdrm_nouveau with libdrmBen Skeggs
2009-02-04nouveau: bring in new mm api definitions, without the actual mm codeBen Skeggs
Use of the new bits is guarded with a mm_enabled=0 hardcode.
2009-02-03modetest: Use cairo (if available) to paint a better pattern.Kristian Høgsberg
2009-02-03modetest: Don't sleep when just dumping state, wait for key for modeset.Kristian Høgsberg
2009-02-03modetest: Handle setting modes on multiple crtcs with one fb.Kristian Høgsberg
2009-02-03modetest: Use a more interesting test pattern.Kristian Høgsberg
2009-02-02Remove the "nv" driver.Stephane Marchesin
2009-02-02No need to pin buffer anymore in modetest.cKristian Høgsberg
2009-01-29nouveau: don't save channel context if it has recently become invalidStuart Bennett
Bug exposed by DDX change d9da090c
2009-01-29nouveau: no suspend support for nv50+Stuart Bennett
2009-01-27Clean up README for the current state of kernel module affairs.Eric Anholt
Bug #19608.
2009-01-27intel: don't count fences on 965 and later, as they don't use them.Eric Anholt
2009-01-27intel: Fix under-counting of fences registers required in check_aperture.Eric Anholt
2009-01-27intel: libdrm support for fence management in execbufJesse Barnes
This patch tries to use the available fence count to figure out whether a given batch can succeed or not (just like the aperture check). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-01-27drm compat: fix euid for >=2.6.28Pekka Paalanen
drm_fops.c reads the current process' EUID directly from task_struct. Apparently starting in 2.6.28-rc4 this fails to build. In Linus' tree, commit b6dff3ec5e116e3af6f537d4caedcad6b9e5082a "CRED: Separate task security context from task_struct" moves the euid field from task_struct to another struct. Earlier commit 9e2b2dc4133f65272a6d3c5dcb2ce63f8a87cae9 "CRED: Introduce credential access wrappers" implements the wrapper macros to access e.g. euid. This is in 2.6.27-rc4, and this contains the definition of current_euid() that will be used in the DRM compatibility header for kernels before 2.6.27. That commit also creates <linux/cred.h>, which contains the upstream definition of current_euid(). drm_fops.c is fixed to use current_euid(), and drm_compat.h will offer the compatibility definition for kernels <2.6.27. Signed-off-by: Pekka Paalanen <pq@iki.fi>
2009-01-27nv50: support chipset NV96Ben Skeggs
ctxprog seen in okias' trace identical to one we use on NV94, assuming the initial context values for NV94 will work here too.
2009-01-27nv04-nv40: correct RAMHT sizeBen Skeggs
2009-01-19drm: remove drmstat/dristat from linux-core buildDave Airlie
pointed out by pq
2009-01-14bump version to 2.4.4Eric Anholt
2009-01-14intel: Retry pin ioctl on -EINTR.Eric Anholt
2009-01-13Don't use DRM_BO_FLAG_NO_MOVE in bufmgr fake. It's a ttm flag.Owain G. Ainsworth
It's also unused, so worthless.
2009-01-12Remove drmModeReplaceFb after it was removed from the kernel.Owain G. Ainsworth
It is impossible to replace the original semantics of this call purely in userland, since the fb_id would change. after discussion with Dr_Jakob Signed-Off-By: Owain Ainsworth <oga@openbsd.org> Acked-By: Jakob Bornecrantz <jakob@vmware.com>
(0x00800040+(i*NV03_USER_SIZE)) #define NV03_USER_DMA_PUT__SIZE 16 #define NV10_USER_DMA_PUT__SIZE 32 #define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE)) #define NV03_USER_DMA_GET__SIZE 16 #define NV10_USER_DMA_GET__SIZE 32 #define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE)) #define NV03_USER_REF_CNT__SIZE 16 #define NV10_USER_REF_CNT__SIZE 32 #define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE)) #define NV40_USER_SIZE 0x00001000 #define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE)) #define NV40_USER_DMA_PUT__SIZE 32 #define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE)) #define NV40_USER_DMA_GET__SIZE 32 #define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE)) #define NV40_USER_REF_CNT__SIZE 32 #define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE)) #define NV50_USER_SIZE 0x00002000 #define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE)) #define NV50_USER_DMA_PUT__SIZE 128 #define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE)) #define NV50_USER_DMA_GET__SIZE 128 /*XXX: I don't think this actually exists.. */ #define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE)) #define NV50_USER_REF_CNT__SIZE 128 #define NV03_FIFO_SIZE 0x8000UL #define NV03_PMC_BOOT_0 0x00000000 #define NV03_PMC_BOOT_1 0x00000004 #define NV03_PMC_INTR_0 0x00000100 # define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8) # define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) # define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21) # define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) # define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) # define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26) # define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) #define NV03_PMC_INTR_EN_0 0x00000140 # define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0) #define NV03_PMC_ENABLE 0x00000200 # define NV_PMC_ENABLE_PFIFO (1<< 8) # define NV_PMC_ENABLE_PGRAPH (1<<12) /* Disabling the below bit breaks newer (G7X only?) mobile chipsets, * the card will hang early on in the X init process. */ # define NV_PMC_ENABLE_UNK13 (1<<13) #define NV40_PMC_1700 0x00001700 #define NV40_PMC_1704 0x00001704 #define NV40_PMC_1708 0x00001708 #define NV40_PMC_170C 0x0000170C /* probably PMC ? */ #define NV50_PUNK_BAR0_PRAMIN 0x00001700 #define NV50_PUNK_BAR_CFG_BASE 0x00001704 #define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) #define NV50_PUNK_BAR1_CTXDMA 0x00001708 #define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) #define NV50_PUNK_BAR3_CTXDMA 0x0000170C #define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) #define NV50_PUNK_UNK1710 0x00001710 #define NV04_PBUS_PCI_NV_1 0x00001804 #define NV04_PBUS_PCI_NV_19 0x0000184C #define NV04_PTIMER_INTR_0 0x00009100 #define NV04_PTIMER_INTR_EN_0 0x00009140 #define NV04_PTIMER_NUMERATOR 0x00009200 #define NV04_PTIMER_DENOMINATOR 0x00009210 #define NV04_PTIMER_TIME_0 0x00009400 #define NV04_PTIMER_TIME_1 0x00009410 #define NV04_PTIMER_ALARM_0 0x00009420 #define NV50_I2C_CONTROLLER 0x0000E054 #define NV04_PFB_CFG0 0x00100200 #define NV04_PFB_CFG1 0x00100204 #define NV40_PFB_020C 0x0010020C #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) #define NV10_PFB_TILE__SIZE 8 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) #define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16)) #define NV10_PFB_CLOSE_PAGE2 0x0010033C #define NV40_PFB_TILE(i) (0x00100600 + (i*16)) #define NV40_PFB_TILE__SIZE_0 12 #define NV40_PFB_TILE__SIZE_1 15 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) #define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16)) #define NV40_PFB_UNK_800 0x00100800 #define NV04_PGRAPH_DEBUG_0 0x00400080 #define NV04_PGRAPH_DEBUG_1 0x00400084 #define NV04_PGRAPH_DEBUG_2 0x00400088 #define NV04_PGRAPH_DEBUG_3 0x0040008c #define NV10_PGRAPH_DEBUG_4 0x00400090 #define NV03_PGRAPH_INTR 0x00400100 #define NV03_PGRAPH_NSTATUS 0x00400104 # define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) # define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) # define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) # define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) # define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) # define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) # define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) # define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) #define NV03_PGRAPH_NSOURCE 0x00400108 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0) # define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1) # define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2) # define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3) # define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4) # define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5) # define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6) # define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7) # define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8) # define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9) # define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) # define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) # define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) # define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) # define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) # define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) # define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) #define NV03_PGRAPH_INTR_EN 0x00400140 #define NV40_PGRAPH_INTR_EN 0x0040013C # define NV_PGRAPH_INTR_NOTIFY (1<< 0) # define NV_PGRAPH_INTR_MISSING_HW (1<< 4) # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) # define NV_PGRAPH_INTR_ERROR (1<<20) #define NV10_PGRAPH_CTX_CONTROL 0x00400144 #define NV10_PGRAPH_CTX_USER 0x00400148 #define NV10_PGRAPH_CTX_SWITCH1 0x0040014C #define NV10_PGRAPH_CTX_SWITCH2 0x00400150 #define NV10_PGRAPH_CTX_SWITCH3 0x00400154 #define NV10_PGRAPH_CTX_SWITCH4 0x00400158 #define NV10_PGRAPH_CTX_SWITCH5 0x0040015C #define NV04_PGRAPH_CTX_SWITCH1 0x00400160 #define NV10_PGRAPH_CTX_CACHE1 0x00400160 #define NV04_PGRAPH_CTX_SWITCH2 0x00400164 #define NV04_PGRAPH_CTX_SWITCH3 0x00400168 #define NV04_PGRAPH_CTX_SWITCH4 0x0040016C #define NV04_PGRAPH_CTX_CONTROL 0x00400170 #define NV04_PGRAPH_CTX_USER 0x00400174 #define NV04_PGRAPH_CTX_CACHE1 0x00400180 #define NV10_PGRAPH_CTX_CACHE2 0x00400180 #define NV03_PGRAPH_CTX_CONTROL 0x00400190 #define NV03_PGRAPH_CTX_USER 0x00400194 #define NV04_PGRAPH_CTX_CACHE2 0x004001A0 #define NV10_PGRAPH_CTX_CACHE3 0x004001A0 #define NV04_PGRAPH_CTX_CACHE3 0x004001C0 #define NV10_PGRAPH_CTX_CACHE4 0x004001C0 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0 #define NV40_PGRAPH_CTXCTL_0304 0x00400304 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 #define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff #define NV40_PGRAPH_CTXCTL_0310 0x00400310 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 #define NV40_PGRAPH_CTXCTL_030C 0x0040030c #define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 #define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 #define NV40_PGRAPH_CTXCTL_CUR 0x0040032c #define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 #define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF #define NV03_PGRAPH_ABS_X_RAM 0x00400400 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480 #define NV03_PGRAPH_X_MISC 0x00400500 #define NV03_PGRAPH_Y_MISC 0x00400504 #define NV04_PGRAPH_VALID1 0x00400508 #define NV04_PGRAPH_SOURCE_COLOR 0x0040050C #define NV04_PGRAPH_MISC24_0 0x00400510 #define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 #define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 #define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C #define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 #define NV03_PGRAPH_CLIPX_0 0x00400524 #define NV03_PGRAPH_CLIPX_1 0x00400528 #define NV03_PGRAPH_CLIPY_0 0x0040052C #define NV03_PGRAPH_CLIPY_1 0x00400530 #define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 #define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 #define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C #define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 #define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 #define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 #define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 #define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 #define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 #define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C #define NV04_PGRAPH_MISC24_1 0x00400570 #define NV04_PGRAPH_MISC24_2 0x00400574 #define NV04_PGRAPH_VALID2 0x00400578 #define NV04_PGRAPH_PASSTHRU_0 0x0040057C #define NV04_PGRAPH_PASSTHRU_1 0x00400580 #define NV04_PGRAPH_PASSTHRU_2 0x00400584 #define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 #define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C #define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 #define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 #define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 #define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C #define NV04_PGRAPH_FORMAT_0 0x004005A8 #define NV04_PGRAPH_FORMAT_1 0x004005AC #define NV04_PGRAPH_FILTER_0 0x004005B0 #define NV04_PGRAPH_FILTER_1 0x004005B4 #define NV03_PGRAPH_MONO_COLOR0 0x00400600 #define NV04_PGRAPH_ROP3 0x00400604 #define NV04_PGRAPH_BETA_AND 0x00400608 #define NV04_PGRAPH_BETA_PREMULT 0x0040060C #define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 #define NV04_PGRAPH_FORMATS 0x00400618 #define NV10_PGRAPH_DEBUG_2 0x00400620 #define NV04_PGRAPH_BOFFSET0 0x00400640 #define NV04_PGRAPH_BOFFSET1 0x00400644 #define NV04_PGRAPH_BOFFSET2 0x00400648 #define NV04_PGRAPH_BOFFSET3 0x0040064C #define NV04_PGRAPH_BOFFSET4 0x00400650 #define NV04_PGRAPH_BOFFSET5 0x00400654 #define NV04_PGRAPH_BBASE0 0x00400658 #define NV04_PGRAPH_BBASE1 0x0040065C #define NV04_PGRAPH_BBASE2 0x00400660 #define NV04_PGRAPH_BBASE3 0x00400664 #define NV04_PGRAPH_BBASE4 0x00400668 #define NV04_PGRAPH_BBASE5 0x0040066C #define NV04_PGRAPH_BPITCH0 0x00400670 #define NV04_PGRAPH_BPITCH1 0x00400674 #define NV04_PGRAPH_BPITCH2 0x00400678 #define NV04_PGRAPH_BPITCH3 0x0040067C #define NV04_PGRAPH_BPITCH4 0x00400680 #define NV04_PGRAPH_BLIMIT0 0x00400684 #define NV04_PGRAPH_BLIMIT1 0x00400688 #define NV04_PGRAPH_BLIMIT2 0x0040068C #define NV04_PGRAPH_BLIMIT3 0x00400690 #define NV04_PGRAPH_BLIMIT4 0x00400694 #define NV04_PGRAPH_BLIMIT5 0x00400698 #define NV04_PGRAPH_BSWIZZLE2 0x0040069C #define NV04_PGRAPH_BSWIZZLE5 0x004006A0 #define NV03_PGRAPH_STATUS 0x004006B0 #define NV04_PGRAPH_STATUS 0x00400700 #define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 #define NV04_PGRAPH_TRAPPED_DATA 0x00400708 #define NV04_PGRAPH_SURFACE 0x0040070C #define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C #define NV04_PGRAPH_STATE 0x00400710 #define NV10_PGRAPH_SURFACE 0x00400710 #define NV04_PGRAPH_NOTIFY 0x00400714 #define NV10_PGRAPH_STATE 0x00400714 #define NV10_PGRAPH_NOTIFY 0x00400718 #define NV04_PGRAPH_FIFO 0x00400720 #define NV04_PGRAPH_BPIXEL 0x00400724 #define NV10_PGRAPH_RDI_INDEX 0x00400750 #define NV04_PGRAPH_FFINTFC_ST2 0x00400754 #define NV10_PGRAPH_RDI_DATA 0x00400754 #define NV04_PGRAPH_DMA_PITCH 0x00400760 #define NV10_PGRAPH_FFINTFC_ST2 0x00400764 #define NV04_PGRAPH_DVD_COLORFMT 0x00400764 #define NV04_PGRAPH_SCALED_FORMAT 0x00400768 #define NV10_PGRAPH_DMA_PITCH 0x00400770 #define NV10_PGRAPH_DVD_COLORFMT 0x00400774 #define NV10_PGRAPH_SCALED_FORMAT 0x00400778 #define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 #define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 #define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 #define NV04_PGRAPH_PATT_COLOR0 0x00400800 #define NV04_PGRAPH_PATT_COLOR1 0x00400804 #define NV04_PGRAPH_PATTERN 0x00400808 #define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 #define NV04_PGRAPH_CHROMA 0x00400814 #define NV04_PGRAPH_CONTROL0 0x00400818 #define NV04_PGRAPH_CONTROL1 0x0040081C #define NV04_PGRAPH_CONTROL2 0x00400820 #define NV04_PGRAPH_BLEND 0x00400824 #define NV04_PGRAPH_STORED_FMT 0x00400830 #define NV04_PGRAPH_PATT_COLORRAM 0x00400900 #define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16)) #define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16)) #define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16)) #define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16)) #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) #define NV04_PGRAPH_U_RAM 0x00400D00 #define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16)) #define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16)) #define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16)) #define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16)) #define NV04_PGRAPH_V_RAM 0x00400D40 #define NV04_PGRAPH_W_RAM 0x00400D80 #define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 #define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 #define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 #define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C #define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 #define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 #define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 #define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C #define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60