renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

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author	Chris Wilson <chris@chris-wilson.co.uk>	2009-11-30 20:02:05 +0000
committer	Chris Wilson <chris@chris-wilson.co.uk>	2009-11-30 20:02:05 +0000
commit	60aa803dc76bbdfac72da4de4cdc3018717b0884 (patch)
tree	2f2703df285f9180218a01673e96ee82b257fe6b /tests/drmtest.h
parent	6f66de982ad6ee6967ec61a7399e600bdd9e5887 (diff)

intel: Only store a buffer in the cache if it is retained.

If the kernel immediately frees the backing store for a buffer when marking it purgeable, then there is not point adding to the cache. Free it immediately, instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Diffstat (limited to 'tests/drmtest.h')

0 files changed, 0 insertions, 0 deletions

PLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef __SAVAGE_DRV_H__ #define __SAVAGE_DRV_H__ /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ enum savage_family { S3_UNKNOWN = 0, S3_SAVAGE3D, S3_SAVAGE_MX, S3_SAVAGE4, S3_PROSAVAGE, S3_TWISTER, S3_PROSAVAGEDDR, S3_SUPERSAVAGE, S3_SAVAGE2000, S3_LAST }; #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ || (chip==S3_PROSAVAGE) \ || (chip==S3_TWISTER) \ || (chip==S3_PROSAVAGEDDR)) #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ ||(chip==S3_PROSAVAGEDDR)) /* flags */ #define SAVAGE_IS_AGP 1 typedef struct drm_savage_private { drm_savage_sarea_t *sarea_priv; enum savage_family chipset; unsigned flags; } drm_savage_private_t; #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ #endif /* end #ifndef __SAVAGE_DRV_ */


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