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authorMichel Dänzer <michel@tungstengraphics.com>2007-02-28 12:33:56 +0100
committerMichel Dänzer <michel@tungstengraphics.com>2007-02-28 12:33:56 +0100
commitfd0fed3f1e10d7ff1205a485621767b650c6f5ff (patch)
treeeda7d04974fe1412cde7f1ade86b4e9c644f4dc9 /linux-core/drm_sarea.h
parent1a0d890a42bee78177ad45d5e5956d2c3c4fcdc7 (diff)
i915: Fix test for synchronous flip affecting both pipes.
Diffstat (limited to 'linux-core/drm_sarea.h')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-23 06:56:44 +0000
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#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"

static void
nv04_instmem_determine_amount(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	/* Figure out how much instance memory we need */
	if (dev_priv->card_type >= NV_40) {
		/* We'll want more instance memory than this on some NV4x cards.
		 * There's a 16MB aperture to play with that maps onto the end
		 * of vram.  For now, only reserve a small piece until we know
		 * more about what each chipset requires.
		 */
		dev_priv->ramin_rsvd_vram = (1*1024* 1024);
	} else {
		/*XXX: what *are* the limits on <NV40 cards?, and does RAMIN
		 *     exist in vram on those cards as well?
		 */
		dev_priv->ramin_rsvd_vram = (512*1024);
	}
	DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10);

	/* Clear all of it, except the BIOS image that's in the first 64KiB */
	for (i=(64*1024); i<dev_priv->ramin_rsvd_vram; i+=4)
		NV_WI32(i, 0x00000000);
}

static void
nv04_instmem_configure_fixed_tables(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	/* FIFO hash table (RAMHT)
	 *   use 4k hash table at RAMIN+0x10000
	 *   TODO: extend the hash table
	 */
	dev_priv->ramht_offset = 0x10000;
	dev_priv->ramht_bits   = 9;
	dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
	DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
						  dev_priv->ramht_size);

	/* FIFO runout table (RAMRO) - 512k at 0x11200 */
	dev_priv->ramro_offset = 0x11200;