renesas/drm.git/radeon, branch android libdrm, cloned from git://anongit.freedesktop.org/mesa/drm radeon: fix tile_split of 128-bit surface formats with 8x MSAA 2012-10-26T18:00:59+00:00 Marek Olšák maraeo@gmail.com 2012-10-16T00:08:02+00:00 e32fff8e9ea8d522679eaab21a9555cab134fb36 The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
The calculation led to the number 8192, which is too high.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: fix unused-function warning 2012-10-24T16:25:58+00:00 Andreas Boll andreas.boll.dev@gmail.com 2012-08-28T10:49:45+00:00 bc494b310d76f701798aee0f2b0b472d608cbfaf radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but not used [-Wunused-function] Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but
not used [-Wunused-function]

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: add some new SI pci ids 2012-10-16T16:58:39+00:00 Alex Deucher alexander.deucher@amd.com 2012-10-16T16:58:39+00:00 a4cb7233a8da171e53b48b376be5c1265c29a612 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI 2012-10-06T03:45:56+00:00 Marek Olšák maraeo@gmail.com 2012-09-30T17:20:04+00:00 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: don't force stencil tile split to 0 2012-10-06T03:45:26+00:00 Marek Olšák maraeo@gmail.com 2012-09-30T17:19:13+00:00 77413e77b82a5d800c86b7d3b864d6cc797721c9 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: don't take the stencil-specific codepath for buffers without stencil 2012-10-03T15:52:44+00:00 Marek Olšák maraeo@gmail.com 2012-09-29T13:10:33+00:00 b3d90bbc1d43bb11d8de25109f403b1b30533c34 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI. 2012-09-06T13:25:13+00:00 Michel Dänzer michel.daenzer@amd.com 2012-09-05T16:44:45+00:00 b925022a3e4616665b388a78abab4e3270b4b4ec Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Another corner case that isn't well-explained yet.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
radeon: Memory footprint of SI mipmap base level is padded to powers of two. 2012-09-06T13:24:44+00:00 Michel Dänzer michel.daenzer@amd.com 2012-09-04T16:53:55+00:00 45083e6d36125c64267c917da3d81e1e144ed33d Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
radeon: Fix layout of linear aligned mipmaps on SI. 2012-09-05T16:47:49+00:00 Michel Dänzer michel.daenzer@amd.com 2012-08-31T17:29:33+00:00 8572444fd0cda3e7b9557c09d2d0f7a9e049a2e7 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
radeon: align r600 msaa buffers to a multiple of macrotile size * num samples 2012-08-24T14:51:14+00:00 Marek Olšák maraeo@gmail.com 2012-08-20T15:15:15+00:00 853429b939c792c4bc0bc91fdef696e3251b88d9 I am not sure whether this is needed, but better be safe than sorry. 
I am not sure whether this is needed, but better be safe than sorry.