renesas/drm.git/intel, branch live libdrm, cloned from git://anongit.freedesktop.org/mesa/drm intel/aub: Implement a way to specify the output .aub filename 2013-06-10T16:52:39+00:00 Damien Lespiau damien.lespiau@intel.com 2013-02-20T12:11:49+00:00 fbd106ad76b0ee33814f6a5b94efaa0b067ec2af Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/aub: Return early if we disable aub dumps 2013-06-10T16:52:34+00:00 Damien Lespiau damien.lespiau@intel.com 2013-02-20T12:11:50+00:00 1e4f63bbc8e9a23c90745e10027e2772bab15038 No need to prepare the .aub header and dump in that case, it'll be done with the next call with true. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> 
No need to prepare the .aub header and dump in that case, it'll be
done with the next call with true.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/aub: Sync the AUB defines with mesa's 2013-06-10T16:51:17+00:00 Damien Lespiau damien.lespiau@intel.com 2013-02-20T12:11:48+00:00 59257580666cf5f5916bf989d94bace774030bd5 Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel: Adding more reserved PCI IDs for Haswell. 2013-06-05T22:31:16+00:00 Rodrigo Vivi rodrigo.vivi@gmail.com 2013-05-13T20:48:40+00:00 1669a67d063e82a58dae4d906015172d471e9a2a At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> 
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.

Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
intel: Fix Haswell GT3 names. 2013-06-05T22:30:36+00:00 Rodrigo Vivi rodrigo.vivi@gmail.com 2013-05-13T20:48:39+00:00 150c3555e7ba53f6ad2d3970cca8e4d5970410aa When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> 
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel: Add support for VEBOX ring (v2) 2013-04-27T18:31:22+00:00 Xiang, Haihao haihao.xiang@intel.com 2012-11-14T04:46:39+00:00 011999927f76a7e9ba8f047fae4b4e084da6c2c3 v2: Fix the test for has_vebox Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> 
v2: Fix the test for has_vebox

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel-decode: Fix gen6 HIER_DEPTH_BUFFER decoding 2013-04-04T07:59:20+00:00 Daniel Vetter daniel.vetter@ffwll.ch 2013-04-03T16:25:12+00:00 b7bb9e929786eb8bae86cf50f54dcb94bfa7ad46 It accidentally used the cmd id for the gen7 command and had an outdated lenght field. Spotted while trying to make sense of an ivb error_state from mesa 7.11 ... Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> 
It accidentally used the cmd id for the gen7 command and had an
outdated lenght field. Spotted while trying to make sense of an ivb
error_state from mesa 7.11 ...

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
intel: Fix Haswell CRW PCI IDs. 2013-03-28T20:24:15+00:00 Kenneth Graunke kenneth@whitecape.org 2013-03-01T23:37:01+00:00 ca678bc073462623cfc89dea80271bc361f1655f The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1).  This also meant no support for GT1 at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
intel_chipset: Fix up VLV confusion 2013-03-27T09:13:44+00:00 Ville Syrjälä ville.syrjala@linux.intel.com 2013-02-18T18:50:01+00:00 93d12593e5f1b251a09b112d7beaf5cfca026896 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> 
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_chipset: Use parens around macro arguments 2013-03-27T09:13:44+00:00 Ville Syrjälä ville.syrjala@linux.intel.com 2013-02-18T18:22:21+00:00 6e55fd7dee48dabcd46939df1aa8729eba426298 Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> 
Protect the macro argument evaluations with parens.

This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>